8662SXX Search Results

GS8662S36E-167

Abstract: GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333 24 c 1024 w
Contextual Info: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

GS818

Contextual Info: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

AN1021

Contextual Info: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaSIO Interface

Contextual Info: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

GS8662S18E-167I

Abstract: GS8662S36E-167 GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333
Contextual Info: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: GS8662S08/09/18/36E-250/200/167 250 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 SigmaSIO DDR-II SRAM 165-Bump BGA Commercial Temp Industrial Temp A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K.

Contextual Info: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaSIO Interface

Contextual Info: Preliminary GS8662S08/09/18/36BD-333/300/250/200/167 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaSIO Interface

Contextual Info: GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 SigmaSIO DDR-II SRAM 165-Bump BGA Commercial Temp Industrial Temp A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K.

AN1021

Abstract: GS8662S36E-167 GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333
Contextual Info: GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 SigmaSIO DDR-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO™ DDR-II Interface • JEDEC-standard pinout and package