82C5SA Search Results

82c56

Contextual Info: in te i 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most O tter Microprocessor» • Control Word Read-Back Capability . Direct Bit S .t /R .« t Capability and 80186/188 « & " » £ £ £ ''• * “ ‘' ° Port ° UtpUtS

Contextual Info: HARRIS SEHICOND SECTOR TS D e I 43DE271 □OlDTflT 1 T ~ 3 3 - 0 3 h a r r is 8 2 C 5 5 A CMOS Programmable Peripheral Interface Features • • • • • • • • • • Pinouts * Pin Compatible with NMOS 8255A 24 Programmable I/O Pins Fully TTL Compatible

82C55AC

Abstract: C82C55A 82CSSA M62C M62C55A-5 m82c55a-5 I82C55A I82C55A-5 m82c55a 55FB
Contextual Info: J D H A R R I S CMOS Programmable Peripheral Interface Features • • • • • • • • • • Pinouts * Pin C om patible with N M O S 8255A 24 Program m able I/O Pins Fully TTL Com patible High Speed, N o “W ait State” Operation w ith 5M H z and 8M H z 80C 86/80C 88

74c920

Abstract: 74C929 74C930 1 phase SCR TRIGGER PULSE TRANSFORMER d8259ac zener chn 848 P8255 interfacing 8289 with 8086 HD-6402C-9 harris semiconductor cmos
Contextual Info: ADVANCED SEMICONDUCTOR DEVIC^S P T Y LTD y I JOHANNESBURG 2000 TEL. 802-5820 DIGITAL DATA BOOK Part of the Harris Spectrum of Integrated Circuits HARRIS $ 5 .0 0 1 9 8 4 Harris C M O S Digital Data Book Harris Semiconductor CMOS Digital Products Division's

80C55A

Abstract: B2C55A
Contextual Info: 00 HARRIS 82C 55A /883 C M O S Programmable Peripheral Interface june 1989 Features D escription • This Circuit is Processed in Accordance to Mil-Std883 and is fully Conformant Under the Provisions of Paragraph 1.2.1 The Harris 82C55A/883 is a high performance CMOS

182c55a

Abstract: 82C55A-2
Contextual Info: in te i 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most Other Microprocessors Control Word Read-Back Capability High Speed, “Zero Wait State” Operation with 8 MHz 8086/88 and 80186/188 2.5 mA DC Drive Capability on all I/O

Contextual Info: in te i 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most Other Microprocessors • Control Word Read-Back Capability B Direct Bit Set/Reset Capability High Speed, “Zero Wan State” Operation with 8 MHz 8086/88 and 80186/188

Contextual Info: 00 HARRIS 82C55A/883 C M O S Program m able Peripheral Interface June 1989 D escrip tio n Features • This Circuit is Processed in Accordance to M il-S td 883 and is fully Conform ant U nder the Provisions of Paragraph 1.2.1 • Pin Com patible with NMOS 8255A

82C55AC

Abstract: 82055A 82C55A-2 8255A ic details Burroughs 82c55AP ic 8255A 8085AH 82C55A 82c55a2
Contextual Info: 82C55A 82C55A CM O S Programmable Peripheral Interface ¡APX86 Family DISTINCTIVE CHARACTERISTICS • • • • Pin com patible w ith NMOS 8255A 24 program m able I/O pins Fully TTL com patible Bus hold circuitry on all I/O ports - elim inates pull-up resistors

SCR 131- 6 WJ 65

Abstract: 82C55A-2 82C55AM 82g55a S55A 8255A 8255A intel microprocessor block diagram and pin ic 8255A intel 8255A ud 1803 IC
Contextual Info: ir v to l. “ 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE • Compatible with all Intel and Most Other Microprocessors . H W SpMd, 'Zero Walt State" Operation with 8 MHz 8086/88 and ■ ■ 80186/188 ■ Control Word Read-Back Capability r ■ “ " *

82c55ac

Abstract: DFI01 pc2ac
Contextual Info: 82C55A 33 HARRIS CMOS Programmable Peripheral Interface Features Pinouts * • P in C o m p a tib le w ith N M O S 82S 5 A TO P V IE W • 2 4 P ro g ra m m a b le I / O Pins • F u lly T T L C o m p a tib le PA3 C 1 • H ig h S p e e d , N o ' W a lt S ta te ” O p e ra tio n w ith 5 M H z a n d 8 M H z 8 0 C 8 6 /8 0 C 8 8

Contextual Info: ¡Si HARRIS 82C55A S E M I C O N D U C T O R 1 / ^ 1 CMOS Programmable Peripheral Interface February 1992 Features Description • Pin Compatible with NMOS 8255A The Harris 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a

Contextual Info: a 82C55A HARRIS SEM ICONDUCTOR CMOS Programmable Peripheral Interface August 1996 Features Description • Pin Compatible with NMOS 8255A The Harris 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process Scaled SAJI IV . It

82C55AC

Abstract: 82c55AP C82C55A
Contextual Info: H A R R 82C55A IS S E M I C O N D U C T O R CMOS Programmable Peripheral Interface February 1992 Features Description • Pi n Compatible with NMOS 8255A The Harris 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a

80186 microprocessors block diagram and pin diagrams

Abstract: block and pin diagram of 8086 PIN DIAGRAM OF 80186 8086 pinout diagram 80186
Contextual Info: 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE • ■ ■ Compatible with all Intel and Most Other Microprocessors Control Word Read-Back Capability High Speed, “Zero Wait State” Operation with 8 MHz 8086/88 and 80186/188 2.5 mA DC Drive Capability on all I/O

8255A-5

Abstract: MSM82C55A MSM82C55A-2RS MSM82C55A-2VJS MSM82C55A2RS MSM82C55A-5
Contextual Info: 3 OKI o n semiconductor MSM82C55A-2RS/GS/VJS CMOS PROGRAMMABLE PERIPHERAL INTERFACE GENERAL DESCRIPTION The M S M 8 2 C 5 5 A is a p rogram m able universal I/O in te rfa c e d evice w h ic h ope ra te s as h ig h speed and on lo w p o w e r c o n su m p tio n due to 3 ¡i silico n g ate C M OS te c h n o lo g y . It is th e b e s t f i t as an I/O p o rt in a sy s te m