82C288 Search Results

intel 80286 pin function

Abstract: MB4-200
Contextual Info: in te * 82C288 BUS CONTROLLER FOR 80286 PROCESSORS 82C288-12, 82C288-10, 82C288-8 • P rovides Com m ands and Controls for Local and System Bus ■ W ide Flexibility In System C onfigurations ■ High Speed CHMOS III Technology ■ Fully Static D evice

IEEE-796

Abstract: ic 80286
Contextual Info: in te i 82C288 BUS CONTROLLER FOR 80286 PROCESSORS 82C288-12,82C288-10, 82C288-8 Provides Commands and Controls for • Fully Static Device Local and System Bus Wide Flexibility in System Configurations a Available in 20 Pin PLCC (Plastic Leaded Chip Carrier) and 20 Pin Cerdip

FT838

Abstract: ft831 82C288 SAB 80286 16 N FT832
Contextual Info: SAB 82C288 Bus Controller for SAB 80286 Processors SAB 82C288 up to 16 MHz SAB 82C288-12 up to 25 MHz SAB 82C288-1 up to 20 MHz • P ro vid e s c o m m a n d s and c o n tro l fo r loca l and s y s te m bus • O p tim a l M u ltib u s -c o m p a tib le tim in g

Contextual Info: 82C288/883 Bus Controller For 80C286 Processors June 1989 Features Pinout • Compatible with NMOS 82288 2 0 PIN C ER A M IC DIP TO P VIEW • Fully Static CMOS Design for Low Pow er Operation * IC C S B = 10 jA Maximum ftEiibv ► IC C O P = 1mA/MHz CLK • Provides Commands and Control for Local and System Bus

82289

Abstract: BD004
Contextual Info: 82C288 82C288 BUS CONTROLLER FOR iAPX 286 PROCESSORS PRELIMINARY DISTINCTIVE CHARACTERISTICS • Provides Commands and Control for Local and Sys­ tem Bus • Offers Wide Flexibility in System Configurations • Flexible Command Timing • Optional Multibus* Compatible Timing

Contextual Info: 82C288/883 2 HARRIS Bus Controller For 80C286 Processors Ju n e 19 89 P in o u t Features 20 PIN CERAMIC DIP • Com patible with NMOS 8 2 288 T O P V IE W • Fully Static CMOS Design for Low Power Operation . * IC C S 8 = 10pA Maximum Zi v c c ffEÄo?

LCC 18 Pin Package

Contextual Info: HARRIS SEMICOND SECTOR 1LE D • 4302271 0QlS04b 5 ■ £D HARRIS 82C288/883 T-S^-SS-oS June 1989 Bus Controller For 80C 286 Processors P inout Features • Compatible with NM O S 82288 20 PIN CERAMIC DIP TOP VIEW • Fully S tatic C M O S Design for Low Po w er Operation

IEEE-796

Abstract: 82289 aeks iAPX 286 82C288 82C288-10 82C288-8
Contextual Info: 82C288 82C288 Bus Controller for iAPX 286 Processors DISTINCTIVE CHARACTERISTICS • • • • Provides commands and control for local and sys­ tem bus Offers wide flexibility in system configurations Flexible command timing Optional Multibus* compatible timing

80286 address decoder

Abstract: 82C288 IEEE-796 82C284 80286 addressing modes 80286 intel 80286 intel 80286 pin diagram interfacing of memory devices with 80286 82C288-10
Contextual Info: 82C288 BUS CONTROLLER FOR 80286 PROCESSORS 82C288-12 82C288-10 82C288-8 Y Provides Commands and Controls for Local and System Bus Y Wide Flexibility in System Configurations Y High Speed CHMOS III Technology Y Fully Compatible with the HMOS 82288 Y Fully Static Device

Contextual Info: VLSI Technology, inc . VL82C201 PC/AT-COMPATIBLE SYSTEM CONTROLLER FEATURES DESCRIPTION • Fully compatible with IBM PC/AT-type designs The VL82C201 PC/AT-Compatible System Controller replaces an 82C284 Clock Controller and an 82C288 Bus Controller both are used in ‘286-based

i80c286

Abstract: 80286 address decoder microprocessor 80286 internal architecture 80C286 80C286-10 80C286-12 80C286-16 80C286-20 80C286-25 80C86
Contextual Info: 80C286 High Performance Microprocessor with Memory Management and Protection March 1997 Features Description • Compatible with NMOS 80286 • Wide Range of Clock Rates - DC to 25MHz 80C286-25 - DC to 20MHz (80C286-20) - DC to 16MHz (80C286-16) - DC to 12.5MHz (80C286-12)

AEN 6

Abstract: 80C286 80C86 80C88 82C237 82C37A 82C82 CP82C237 CS82C237 IP82C237
Contextual Info: 82C237 CMOS High Performance Programmable DMA Controller March 1997 Features Description • Fully Compatible with Intersil 82C37A - 82C237 May be Used in 8MHz and 12.5MHz 82C37A Sockets The 82C237 is a modified version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the

Contextual Info: 82C237 HARRIS S E M I C O N D U C T O R CMOS High Performance Programmable DMA Controller March 1997 Features Description • Fully Com patible with Harris 82C37A The 82C237 is a modified version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the

Contextual Info: 82C37A Data Sheet CMOS High Performance Programmable DMA Controller October 25, 2011 FN2967.3 Features • Compatible with the NMOS 8237A The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access DMA controller, fabricated using Intersil’s advanced 2 micron CMOS process. Pin

intel 80C286

Abstract: 82C286 8086 instruction set 80C286 basic architecture of intel 80286 8086 effective address calculation 00FF i80c286 Multitasking of microprocessor 80386 intel intel 8088 memory
Contextual Info: in te i 80C286 CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION • High S p ee d C H M O S III T e c h n o lo g y ■ 12.5 M H z C lo ck R a te ■ Pin fo r Pin, C lo c k fo r C lo ck, and F u n ctio n a lly C o m p atib le w ith th e H M O S 80286

Contextual Info: a Preliminary 80C286 High-Speed CMOS 80286 Microprocessor Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • ■ Ultra high-performance processor —Over 20X performance of 8086 —Over 1,5X performance of 386SX-16* — Comparable performance to 386 at same clock

80287

Abstract: harris 74AC04 ac08 74AC112 80C286 74AC04 74AC08 80C286-16 82C284 82C288
Contextual Info: Harris Semiconductor No. AN120.1 Harris Digital March 1997 Interfacing the 80C286-16 with the 80287-10 Author: Ted Schaufelberger Introduction An important requirement in many systems is the ability to off-load numeric data processing. In an 80C286 system, this

82C37A

Abstract: 82C37A DMA Controller marking db2 5962-9054301MXA 80286 microprocessor features 80286 microprocessor pin out diagram 8088 microprocessor control data bus for 80286 logical block diagram of 80286 microprocessor 80286 Number of registers size
Contextual Info: 82C37A Data Sheet March 20, 2006 CMOS High Performance Programmable DMA Controller FN2967.2 Features • Compatible with the NMOS 8237A The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access DMA controller, fabricated using Intersil’s advanced 2 micron CMOS process. Pin

Contextual Info: HARRIS SENICOND S ECTOR H a r r i H3DSS71 Q D 3 ñ b m MbE D IHAS T 82C237 s S E M I C O N D U C T O R CMOS High Performance Programmable DMA Controller February 1992 Features Description • Fully Compatible with Harris 82C37A - 82C237 May be Used in 8MHz and 12.5MHz 82C37A

Intel 80C286

Contextual Info: in to T 80C286 HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION • High Speed CHMOS III Technology ■ 12.5 MHz Clock Rate ■ Pin for Pin, Clock for Clock, and Functionally Compatible with the HMOS 80286 ■ Available in a Variety of Packages:

MP 9720 ds

Contextual Info: Preliminary 80C286 High-Speed CMOS 80286 Microprocessor Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Ultra high-performance processor —Over 20X performance of 8086 —Over 1.5X performance of 386SX-16* —Comparable performance to 386 at same clock

80C286 microprocessor pin

Contextual Info: 80C286 Advanced Micro Devices High-Speed CMOS 80286 Microprocessor DISTINCTIVE CHARACTERISTICS • Ultra high-performance processor ■ ■ Wide range of clock rates —20 MHz 80C286-20 — 16 MHz (80C286-16) — 12.5 MHz (80C286-12) ■ 100% functionally and pin compatible with

80287

Abstract: 80C286 74AC04 74AC08 74AC112 80C286-16 82C284 82C288 AC112 AN120
Contextual Info: Interfacing the 80C286-16 with the 80287-10 Application Note March 1997 AN120.1 Introduction An important requirement in many systems is the ability to off-load numeric data processing. In an 80C286 system, this can be accomplished with an 80287 numeric co-processor.

Contextual Info: High Performance Microprocessor With Memory Management and Protection Features 80C286 80C2Q6 2 HARRIS Pin Configurations • Compatible with NMOS 80286 Component Pad Views — As viewed from underside of the com o on en t when m ounted on ine board • Static CMOS Design for Low Power Operation