82-RAA 1.6 Search Results

din 82

Abstract: DIN 82-Rge Rge 10-din 82 630 207 Souriau cross reference 8A10 AF5A
Contextual Info: souriau 8A10 Series Description Applications • Audio-miniature connectors with 10 contacts especially designed for transmission of very low current • Bayonet locking system • Solder or straight spills contacts • 5 different orientations • Sealed connector in unmated or mated

din 82

Abstract: 8A10 AF3C AB4C 669-o 10AC2 AF5A af3a
Contextual Info: 8A10 Series Description Applications • Audio-miniature connectors with 10 contacts especially designed for transmission of very low current • Bayonet locking system • Solder or straight spills contacts • 5 different orientations • Sealed connector in unmated or mated

SLP-881A-37

Abstract: HLMP-1002 HLMP-1120 MV5774C 5774c MV5077C SLP-135B-51 MV50640 MV5075C MV57620
Contextual Info: 1 ! & V r, « * flA ft 2 r, • * de«; T .,= 25'C 3 ÍX £•«,* Xi- 1. Ir ÍV m A ; '.V: f i h t f l * '7 , = 25’C "iittt.iíó -íflTl; m.A' niA V n-ffí 70 660 2.5 i 20 1.6 20 35 -55-100 90 660 1.5 20 1.6 20 35 -55-100 i 110 660 1.75 20 1.6 20 35 -55-100

PD48

Abstract: uPD481850GF-A12-JBT
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8M-bit Synchronous GRAM Description The µPD481850 is a synchronous graphics memory SGRAM organized as 128 K words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write

Contextual Info:  $6/&.6 9.ð&026V\QFKURQRXVJUDSKLF5$0 HDWXUHV • Organization - 131,072 words x 32 bits × 2 banks • Fully synchronous - All signals referenced to positive edge of clock • Internal pipeline operation - Column address can be changed every clock cycle

Contextual Info: W971632AF 256K x 32 bit x 2 Banks SGRAM Features • • • • • • • • • • • • • • JEDEC standard 3.3V power supply Up to 143MHz clock frequency 262,144 words x 2 banks x 32 bits 1 Bank Select, Row Address A0~A9, Column Address A0~A7

uPD481850GF-A12-JBT

Abstract: dba1 PD48
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 for Rev.L 8 M-BIT SYNCHRONOUS GRAM 128K-WORD BY 32-BIT BY 2-BANK Description The µPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits × 2 banks random access port.

PD48

Abstract: PD481850 lm 512
Contextual Info: DATA SHEET DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8M-bit Synchronous GRAM Description The µPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4811650 for Rev.E 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The µPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits × 2 banks random access port.

uPD481850

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8 M-bit Synchronous GRAM for Rev.L Description The µPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write

MB3778

Abstract: iw16
Contextual Info: — 304 — MB3778 x-í •u^'zL U-'?$ iJ£P[h]S& tí zl7./u í s. ; K S S O í y y • U — ? S J « I [s ]íS - C , ( ^ « ! * œ a m e < , ín s » *s¡e B ® C 6 S M " C # S . X T - , 7 ' 7 2 w m m i'p c o t f - ? r 7 ^ X f - ; ^ ' ' S — 5"-f 's7<r>&.%<r>2 m m t o & tm m f r ' i U b n z ( t z t i L ,

dba1

Abstract: diode MARKING CODE A9 UPD481 diode MARKING A9
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4811650 for Rev.K 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The µPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits × 2 banks random access port.

UPD4811650GF-A10-9BT

Abstract: 0z1 marking
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4811650 for Rev.K 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The µPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits × 2 banks random access port.

nec 2410

Abstract: transistor NEC D 587 2410 nec
Contextual Info: DATA SHEET SILICON TRANSISTOR 2SC4959 HIGH FREQUENCY LOW NOISE AMPLIFIER NPN SILICON EPITAXIAL TRANSISTOR SUPER MINI MOLD FEATURES • Low Noise, High Gain • Low Voltage Operation • Low Feedback Capacitance C re PACKAGE DIM ENSIONS in m illim eters 2.1

Pixel Magic 35

Contextual Info: Silicon SM84L512K32B MAGIC 512K x 32 SDR SGRAM 06'56\QFKURQRXV*UDSKLFV5$0 0+] Features            Single 3.3 V ± 0.3 power supply 185 / 167 / 143 / 125 MHz maximum clock frequency Dual bank operation Programmable burst type, burst length

Pixel Magic 35

Abstract: Pixel Magic
Contextual Info: Silicon SM84L512K32B MAGIC 512K x 32 SDR SGRAM Preliminary 06'56\QFKURQRXV*UDSKLFV5$0 0+] Features            Single 3.3 V ± 0.3 power supply 167 / 143 / 125 MHz maximum clock frequency Dual bank operation Programmable burst type, burst length

Contextual Info: SCHOTTKY BARRIER DIODE 41MQ50 41MQ60 44A/50~60V FEATURES a Hermetically Sealed Case ° High Reliability Device ° Low Forward Power Loss, High Efficiency ° High Surge Capability »30 Volts through 60 Volts Types Available MAXIMUM RATINGS Voltage Rating \

Contextual Info: SHIELDED MOLDED RF CHOKES 925C SEELIES M iller Number 9250-101 9250-121 9250-151 9250-181 9250-221 9250-271 9250-331 9250-391 9250-471 9250-561 9250-681 9250-821 9250-102 9250-122 9250-152 9250-182 9250-222 9250-272 9250-332 9250-392 9250-472 9250-562 9250-682

ecl83

Abstract: 02X24 Mullard triode ecl83 eCl8 k 1058 PENTODE
Contextual Info: TRIODE PENTODE ECL83 C o m b in e d triode a n d output pentode with sep a rate cathodes intended for use in a u d io fre qu e ncy applications. H E A T E R Suitable fo r parallel o p e ratio n a.c. o r d.c. 6.3 600 V h Ih M O U N T I N G P O S I T IO N V

Contextual Info: AN6884 ICs fo r DISPLAY DRIVER A N 6884 5-Dot LED Driver Circuit • O utline The AN6884 is an integrated circuit designed for driving 5-dot LED and enables a logarithmic dB bar graph display in response to the input signal. The built-in rectifier Amp. is

A45L9332A

Contextual Info: A45L9332A Series Preliminary 256K X 32 Bit X 2 Banks Synchronous Graphic RAM Document Title 256K X 32Bit X 2 Banks Synchronous Graphic RAM Revision History History Issue Date Remark 0.0 Initial issue August 21, 2001 Preliminary 0.1 Update AC and DC data specification

Contextual Info: A45L9332A Series 256K X 32 Bit X 2 Banks Synchronous Graphic RAM Document Title 256K X 32Bit X 2 Banks Synchronous Graphic RAM Revision History History Issue Date Remark 0.0 Initial issue August 21, 2001 Preliminary 0.1 Update AC and DC data specification

A45L9332A

Contextual Info: A45L9332A Series Preliminary 256K X 32 Bit X 2 Banks Synchronous Graphic RAM Document Title 256K X 32Bit X 2 Banks Synchronous Graphic RAM Revision History History Issue Date Remark 0.0 Initial issue August 21, 2001 Preliminary 0.1 Update AC and DC data specification

a45l9332f-6

Abstract: A45L9332 100L
Contextual Info: A45L9332 Series 256K X 32Bit X 2 Banks Synchronous Graphic RAM Document Title 256K X 32Bit X 2 Banks Synchronous Graphic RAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue December 4, 1998 Preliminary 1.0 AC and DC data specification update