8-BIT TTL LATCH Search Results

Contextual Info: □ M nE L A D C -304 8-BIT, 20 MHz LOW POWER, FLASH A/D FEATURES • 8-Bit resolution. • ± '/j LSB non-linearity. • 20 MHz conversion rate. • 8 MHz input bandwidth - 3 dB . • Low power consumption (390 mW). • TTL-compatible. • Single or dual supply operation.

SN74FB2033K

Contextual Info: SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472E – MAY 1994 – REVISED JUNE 1997 D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion

Contextual Info: SN74BCT29853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS002D - SEPTEMBER 1987 - REVISED APRIL 1994 DW OR NT PACKAGE TOP VIEW BiCMOS Process With TTL Inputs and Outputs State-of-the-Art BiCMOS Design Significantly Reduces Standby Current OEA[ A1[ A2[ A3 [

Contextual Info: TLC7226C, TLC7226I, TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą ąą SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 features DW OR N PACKAGE Four 8-Bit D/A Converters Microprocessor Compatible TTL/CMOS Compatible Single Supply Operation Possible

tlc72261

Contextual Info: TLC7226C, TLC7226I, TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą ąą SLAS060E − JANUARY 1995 − REVISED JANUARY 2003 features DW OR N PACKAGE Four 8-Bit D/A Converters Microprocessor Compatible TTL/CMOS Compatible Single Supply Operation Possible

27c040-12

Contextual Info: SMJ27C040 524288 BY 8-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SGMS046B - NOVEMBER 1992 - REVISED SEPTEMBER 1997 Organization . . . 524288 by 8 Bits Single 5-V Power Supply Industry Standard 32-Pin Dual-In-line Package All Inputs/Outputs Fully TTL Compatible

28F512A

Abstract: 28F512A-12
Contextual Info: SMJS514C-FEBRUARY 1 Organization. . . 65536 by 8 Bits All Inputs/Outputs TTL-Compatible TMS28F512A 65536 BY 8-BIT FLASH MEMORY m - REVISED AUGUST 1997 FM PACKAGE TOP VIEW Vgc Tolerance ±10% Maximum Access/Minimum Cycle Time '28F512A-10 100ns ’28F512A-12

Contextual Info: SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion

cmos s-r latch

Abstract: hex latch 74ACQ373 MM74HC259 hex to 7 segment decoder Multiplexer latch octal S-R latch 74ABT373 74AC373 74AC573
Contextual Info: Logic Products by Function Latch Products Logic Product Family Product Description Package Voltage Node DM93L14 Bipolar-TTL Quad Latch DIP 5 DM74LS75 Bipolar-LS Quad Latch DIP SOIC 5 DM74LS259 Bipolar-LS 8-Bit Serial In to Parallel Out Addressable Latches

Contextual Info: SN74BCT29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER S C B S 257- SEPTEMBER 1987 - REVISED NOVEMBER 1993 DW OR NT PACKAGE • BICMOS Process With TTL Inputs and Outputs T O P V IE W • State-of-the-Art BICMOS Design Significantly Reduces Standby Current

74HCT25

Contextual Info: 74HC259; 74HCT259 8-bit addressable latch Rev. 5 — 7 August 2012 Product data sheet 1. General description The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL LSTTL . They are specified in compliance with JEDEC

Contextual Info: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS S C A S Q 2 3 A - D2957, JU L Y 1978- R E V IS E D A P R I L 1993 54ACT11521 . . . J P A C K A G E 74ACT11521 . . . OB, D W O R N P A C K A G E i * Compares Two 8-Bit Words * Inputs Are TTL-Voltage Compatible

Contextual Info: intJ. 80C31BH/80C51BH/87C51 MCS 51 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Automotive • Extended Automotive Temperature Range -40 °C to + 125°C Ambient ■ Programmable Serial Port ■ High Performance CHMOS Process ■ TTL- and CMOS-Compatible Logic

Contextual Info: 74ACT16373 16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTED • ■ ■ HIGH SPEED: tPD = 5.3ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING

SN74ALS29846

Abstract: SN74BCT29846
Contextual Info: SN74BCT29846 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS023C – MARCH 1989 – REVISED APRIL 1994 • • • • • • • • NT PACKAGE TOP VIEW BiCMOS Process With CMOS Inputs and TTL Outputs Substantially Reduces Standby Current Input Has 50-Ω Pullup Resister

A6821SA-T

Abstract: 112D A6821 A6821EA A6821EA-T A6821SA A6821SLW MS-001 A6821SLWTR-T
Contextual Info: A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Features and Benefits Description ▪ 3.3 to 5 V logic supply range ▪ Power on reset POR ▪ To 10 MHz data input rate ▪ CMOS, TTL compatible ▪ –40°C operation available ▪ Schmitt trigger inputs for improved noise immunity

74ACT16245

Abstract: ACT16245
Contextual Info: 74ACT16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS NON INVERTED • ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.)

Contextual Info: TMS28F040 4 194 304-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMJS040-DECEMBER 1992 N PACKAGET Organization . . . 512K x 8 Separately Erasable 32K Byte Blocks Two Power Supplies 5 V and 12 V 100% TTL-Level Control Inputs Fully Automated On-Chip Erase and Byte

Contextual Info: 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR S C A S 1 7 8 - D 3 9 9 0 , D E C E M B E R 1991 - R E V IS E D A P R I L 1 9 9 3 Inputs Are TTL-Voltage Compatible Asynchronous Clear Fully Independent Clock Circuit Simplifies Use

ttl 74100

Abstract: 74100 74100 Latch IC TTL 74100 54100
Contextual Info: TYPES SN54W0, SN74100 8-BIT BISTASIE UTCHES ttl MSI B U L L E T IN N O . D L - S 7211830, D E C E M B E R 1972 " S J 5 Ï Ï » . . . J OR W PACKAGE SNS4100 . . . i OB N PACKAGE TOP VIEW logic FUNCTION TABLE (Each Latch) INPUTS G L H H H X L •^ . .

Contextual Info: 54ACT11874, 74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D3447, MAR CH 1990-R E V IS E D O C TO BER 1990 54A C T 11 8 74 . . . J T P A C K A G E Inputs are TTL-Voltage C om patible 74A C T 11 8 74 . . . D W O R N T P A C K A G E

Contextual Info: Order this data sheet by MC10H681/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10H681 MC100H681 Hex ECL-TTL Transceiver with Latches • Separate Latch Enable Controls for each Direction • ECL Single Ended 50 £1 I/O Port • High Drive TTL I/O Ports • Extra TTL and ECL Power/Ground Pins to Minimize

74ls597

Abstract: 74LS59B
Contextual Info: SN54LS597, SN 54LS598, SN74LS597. SN 74LS59B 8 BIT SHIFT REGISTERS WITH INPUT LATCHES 02635 8-Bit Parallel Storage Register Inputs 'LS597J JA N U A R Y 1981 - REVISED M AR C H 1988 S N 5 4 L S 5 9 7 . . . J OR W P AC KA G E S N 7 4 L S 5 9 7 . . . N P AC KA G E

74LS75

Abstract: 74LS77 751A-02 74ls771 74LS75D
Contextual Info: SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data D input is transferred to