8 NON INVERTING BUFFER Search Results

74LS

Abstract: CD74HC367 CD74HC368 CD74HCT367 CD74HCT368 HC367 HC368 HCT368
Contextual Info: [ /Title CD74 HC367 , CD74 HCT36 7, CD74 HC368 , CD74 HCT36 8 /Subject (High Speed CD74HC367, CD74HCT367, CD74HC368, CD74HCT368 Data sheet acquired from Harris Semiconductor SCHS181 November 1997 High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Low -V o ltag e 1 -8/2.5/3.3V 1 6 -B it Buffer M C 74VC X16 2 4 4 vex With 3.6V-Tolerant Inputs and Outputs 3-State, Non-Inverting The MC74VCX16244 is an advanced performance, non-inverting 16-bit buffer. It is designed for very high-speed, very low-power

Contextual Info: PDU18F FEATURES • • • • • • • •  data 3 delay devices, inc. 8-BIT PROGRAMMABLE DELAY LINE SERIES PDU18F PACKAGES Digitally programmable in 256 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting

PDU18F

Abstract: PDU18F-1 PDU18F-2 PDU18F-3 PDU18F-4 PDU18F-5 PDU18F-6 PDU18F-8
Contextual Info: PDU18F data 3 delay devices, inc. 8-BIT PROGRAMMABLE DELAY LINE SERIES PDU18F FEATURES • • • • • • • •  PACKAGES Digitally programmable in 256 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting

PDU13F

Abstract: PDU13F-1 PDU13F-10 PDU13F-15 PDU13F-2 PDU13F-20 PDU13F-3 PDU13F-5
Contextual Info: PDU13F data 3 delay devices, inc. 3-BIT PROGRAMMABLE DELAY LINE SERIES PDU13F FEATURES • • • • • • • •  PACKAGES Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting

rca 036

Contextual Info: Technical D a ta _ CD54/74AC138, CD54/74AC238 CD54/74ACT138, CD54/74ACT238 A C /A C T A C /A C T 238 138 Advance Information 3-to-8-Line Decoders/Demultiplexers AC/ACT138 - Inverting AC/ACT238 - Non-Inverting FUNCTIONAL DIAGRAM &

Contextual Info: PDU13F FEATURES • • • • • • • •  data 3 delay devices, inc. 3-BIT PROGRAMMABLE DELAY LINE SERIES PDU13F PACKAGES Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting

03602B

Contextual Info: Am2924 Am2924 Three-Line to Eight-Line Decoder/Demultiplexer DISTINCTIVE CHARACTERISTICS • • Advanced Schottky technology Inverting and non-inverting enable inputs GENERAL DESCRIPTION The Am2924 is a 3-line to 8-line decoder/demultiplexer fabricated using advanced Schottky technology. The de­

Contextual Info: TOSHIBA TC74AC540, 541 Octal Bus Buffer with 3-State Outputs 540: Inverting 541 : Non-Inverting Features: High Speed: tpd = 4.0ns typ. at V cc = 5V Low Power Dissipation: lcc = 8^A (max.) at Ta = 25°C High Noise Immunity: V N,H = V N|U = 28% V cc (min.)

amd AM2 PIN LAYOUT

Contextual Info: Am2924 Am2924 Three-Line to Eight-Line Decoder/Demultiplexer DISTINCTIVE CHARACTERISTICS • Advanced Schottky technology • Inverting and non-inverting enable inputs GENERAL DESCRIPTION The Am2924 is a 3-line to 8-line decoder/demultiplexer fabricated using advanced Schottky technology- The de­

DM74ALS151

Abstract: 74ALS DM74ALS DM74ALS151M DM74ALS151N M16A N16A
Contextual Info: DM74ALS151 1 of 8 Line Data Selector/Multiplexer General Description Features This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer

PPG38F

Abstract: PPG38F-10 PPG38F-1 PPG38F-100 PPG38F-2 PPG38F-20 PPG38F-200 PPG38F-5 PPG38F-50
Contextual Info: PPG38F data 3  delay devices, inc. 8-BIT PROGRAMMABLE PULSE GENERATOR SERIES PPG38F FEATURES • • • • • • • • • PACKAGES Digitally programmable in 256 steps Monotonic pulse-width-vs-address variation Rising edge triggered Two separate outputs: inverting & non-inverting

ltm9052

Abstract: LTM-9052 PT2275 PT-2275 PT2265 A733 PT-2275-XX-X ALPs vcr IN4004 IN4148
Contextual Info: PTC PT2275 DECODER DESCRIPTION PT2275 is a remote control decoder paired with PT2265 utilizing CMOS technology. It is housed in a 16 pin DIP and has 8 outputs, data input inverting signal or non-inverting signal control and one bit error check circuit. FEATURES

1 into 16 demultiplexer circuit diagram using 1 i

Abstract: 25ls2539 25LS2548 lmb 50j D-16 25ls2536 F16 - 100 HIP
Contextual Info: Am2924 Am2924 Three-Line to Eight-Line Decoder/Demultiplexer DISTINCTIVE CHARACTERISTICS • • Advanced Schottky technology Inverting and non-inverting enable inputs GENERAL DESCRIPTION The Am 2924 is a 3-line to 8-line decoder/dem ultiplexer fabricated using advanced Schottky technology. The de­

74F245

Abstract: 74F280A 74F657 74F657SPC 75F657SC M24B MS-013 N24C
Contextual Info: Revised August 1999 74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description Features The 74F657 contains eight non-inverting buffers with 3STATE outputs and an 8-bit parity generator/checker. It is

DM74ALS251

Abstract: DM74ALS251M DM74ALS251N M16A N16A
Contextual Info: DM74ALS251 3-STATE 1 of 8 Line Data Selector/Multiplexer General Description Features This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer

7135

Abstract: 71340
Contextual Info: data Programmable Delay Units delay SERIES: PDU-713 T 2L Interfaced 3 BIT devices^ F e a tu re s : • Digitally program m able in 8 delay steps. ■ Fits standard 14 pins DIP socket. ■ Input & outputs fully T T L interfaced & buffered. ■ Two (2) separate outputs; inverting & non-inverting.

MC4049

Abstract: 74hc4050 74hc4049 RCA-CD54
Contextual Info: Technical Data CD54/74HC4049 CD54/74HC4050 File No. 1543 High-Speed CMOS Logic FUNCTIONAL DIAC¡RAM IB - NC V ' V CC-— 3 4 5 _ Hex Buffers, Inverting and Non-Inverting IÖ _ 2 6 7 4* £4 4* * * 14 6 A ia - NC 5A “ r it 1 0 _ . 8 6 N D -

ICSLV218

Abstract: MK74CB218
Contextual Info: ICSLV218 PRELIMINARY INFORMATION Dual 1-to-8 Low Voltage Clock Buffer/Translator Description Features The ICSLV218 is a high-speed clock buffer consisting of two independent single-input to eight-output low-skew, non-inverting clock drivers. • Dual 1:8 clock drivers

74ACQ657

Abstract: 74ACQ657SPC 74ACTQ657 74ACTQ657SC 74ACTQ657SPC M24B MS-013 N24C
Contextual Info: Revised December 1998 74ACQ657 • 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description Features The ACQ/ACTQ657 contains eight non-inverting buffers with 3-STATE outputs and an 8-bit parity generator/

Contextual Info: Revised December 1999 74ACQ657 • 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description Features The ACQ/ACTQ657 contains eight non-inverting buffers with 3-STATE outputs and an 8-bit parity generator/

74ACQ657

Abstract: 74ACQ657SPC 74ACTQ657 74ACTQ657SC 74ACTQ657SPC M24B MS-001 MS-013 N24C
Contextual Info: Revised September 2000 74ACQ657 • 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description Features The ACQ/ACTQ657 contains eight non-inverting buffers with 3-STATE outputs and an 8-bit parity generator/

54ACTQ657

Contextual Info: & Semiconductor 54ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATE Outputs General Description Features The A C TQ 657 contains eight non-inverting buffers with TRI-STATE outputs and an 8-bit parity generator/checker. In­

Contextual Info: FAST CMOS NON-INVERTING BUFFER TRANSCEIVER IDT54/74FCT645 IDT54/74FCT645A FEATURES: DESCRIPTION: • IDT54/74FCT645 equivalent to FAST speed; The IDT54/74FCT645 and IDT54/74FCT645A are 8-bit noninverting buffer transceivers built using advanced CEMOS , a