8 BITS Search Results

Contextual Info: MITSUBISHI LSIs MH1M08TNA-85L,-10L,-12L,-15L/ MH1M08TNA-85H,-10H,-12H,-15H 8 3 8 8 6 0 8 -B IT 1 0 4 8 5 7 6 -W 0 R D B Y 8-BIT CM OS STATIC RAM DESCRIPTION The M H 1 M 0 8 T N A is a 8 3 8 8 6 0 8 bits C M O S static RA M PIN C O N FIG U R ATIO N (TOP V IEW )

Contextual Info: TMS28F008Axy TMS28F800Axy 8 3 8 8 6 0 8 BOOT-BLOCK FLASH MEMORIES _ * * 1048576 By 8 Bits 524288 By 16 Bits Array-Blocking Architecture - Two 8K-Byte Parameter Blocks - One 96K-Byte Main Block - Seven 128K-Byte Main Blocks - One 16K-Byte Protected Boot Block

UG38C3288HSG

Contextual Info: UG38C324 8 8HSG 32M Bytes (8M x 32) DRAM 72Pin SODIMM based on 8M X 8 General Description Features The UG38C324(8)8HSG is a 8,388,8 bits by 32 SODIMM module. The UG38C324(8)8HSG is assembled using 4 pcs of 8M x 8 4K/8K refresh DRAMs in 32-pin TSOP package mounted on

TC518128B

Abstract: TRANSISTOR BFW 11 pin diagram TC518128 TC518128bfl pin diagram of TRANSISTOR BFW 11 TC5181
Contextual Info: TOSHIBA T C 5 1 8 1 2 8 B P L /B S P L /B F L /B F W 1 V B F IL -7 0 /8 0 /1 0 T C 5 1 8 1 2 8 B P iy B S P L /B F V B F W L /B F H r 7 0 iy 8 0 L /1 0 L SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description The TC518128B is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518128B utilizes

Contextual Info: UG58W664 8 8HK(S)G 64M Bytes (8M x 64) DRAM 168Pin DIMM based on 8M x 8 General Description Features The UG58W664(8)8HK(S)G is a 8,388,8 bits by 64 EDO DRAM module. The UG58W664(8)8HK(S)G is assembled using 8 pcs of 8Mx8 4K/8K refresh DRAMs in a 32 pin 400

Contextual Info: UG58W644 8 8HK(S)G 64M Bytes (8M x 64) DRAM 168Pin DIMM based on 8M x 8 General Description Features The UG58W644(8)8HK(S)G is a 8,388,8 bits by 64 EDO DRAM module . The UG58W644(8)8HK(S)G is assembled using 8 pcs of 8Mx8 4K/8K refresh DRAMs in 400mil SOJ

Contextual Info: ADC0808M CMOS ANALOG-TO-DIGITAL CONVERTER WITH 8 CHANNEL MULTIPLEXER D 2 6 4 2 , NOVEMBER 1 9 8 6 -R E V IS E D M A Y 1 9 8 8 ! • Total Unadjusted Error . . . ± 0 .7 5 LSB Max • Resolution of 8 Bits • 100 /is Conversion Time • Ratlometric Conversion

Contextual Info: UG58E644 8 8HK(S)G 64M Bytes (8M x 64) DRAM 168Pin DIMM based on 8M x 8 General Description Features The UG58E644(8)8HK(S)G is a 8,388,8 bits by 64 EDO DRAM module . The UG58E644(8)8HK(S)G is assembled using 8 pcs of 8Mx8 4K/8K refresh DRAMs in 400mil SOJ

26c18

Abstract: ST2100 ST2101 1103h MUX41 TABLE10-1 1185H PCC5
Contextual Info: ST Sitronix ST2100 8 BIT Microcontroller with 2M bytes ROM PRELIMINARY Notice: This is not a final specification. Some parameters are subject to change. 1. FEATURES „ „ „ „ „ „ „ „ „ „ 8-bit static pipeline CPU ROM: 2M x 8 bits RAM: 4K x 8 bits External memory control up to 8M x 8 bits

518128

Abstract: 518128apl TC518128
Contextual Info: TOSHIBA TC518128APL/AFL/AFWL-80LV/10LV/12LV TC518128AFTLS0LV/10LV/12LV SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description T h e T C 5 1 8 1 2 8 A -L V is a 1M bit high speed C M O S p se udo static R AM organized as 131,07 2 w o rd s b y 8 bits. The T C 5 1 8 1 2 8 A -L V

EdE1108ACBG

Abstract: EDE1116ACBG EDE1116ACBG-8E-E EDE1116AC
Contextual Info: DATA SHEET 1G bits DDR2 SDRAM EDE1108ACBG 128M words x 8 bits EDE1116ACBG (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization ⎯ 16M words × 8 bits × 8 banks (EDE1108ACBG) ⎯ 8M words × 16 bits × 8 banks (EDE1116ACBG)

sn74ls380

Contextual Info: Multifunction 8-B it Register S N 5 4 /7 4 L S 3 8 0 Ordering Information Features/ Benefits • 8-bit register for general-purpose interfacing applications PART NUMBER PACKAGE • 8 bits match byte boundaries SN54LS380 JS, F • Bus-structured pinout SN74LS380

SN74LS498

Abstract: 74LS498 SN54/74LS498
Contextual Info: 8-B it Shift Register S N 5 4 /7 4 L S 4 9 8 Features/ Benefits Ordering Information • 8-bit shift register or serial-to-parallel and parallel-toseriai applications • 8 bits match byte boundaries • Bus-structured pinout PART NUMBER PACKAGE SN54LS498

P413

Abstract: p113 p114 100-PIN P310 P311 P312 QFP100-P-1420 SM6004 SM6006
Contextual Info: PRODUCT INFORMATION SM6004/SM6006 16-Bit Single-Chip Microcomputers FEATURES • ROM capacity: – 61,440 x 8-bits SM6004 – 126,976 × 8-bits (SM6006) • RAM capacity: – 2,048 × 8-bits (SM6004) – 3,584 × 8-bits (SM6006) • External memory expansion function

FS70M

Contextual Info: f v T c inc •■ . n d e | TaaaTaT 9 3 8 8 9 2 9 V T C INC_ 99D 0 1 4 3 3 V C 0 0 8 8-BIT 250MHz FLASH A/D CONVERTER . □□01433 D T * 5 / ■‘/¿•'O S ' ADVANCE INFORMATION CONNECTION DIAGRAMS DIP Package - 42-Pln FEATURES • Resolution: 8 bits ±1/2 L.SB

ADC 0809

Abstract: ADC IC 0808 adc 0808 analog to digital converters 0808
Contextual Info: ADC0808, ADC0809 CMOS ANALOG-TO DIGITAL CONVERTERS WITH 8-CHANNEL MULTIPLEXERS D 2 64 2 , JUNE 1 9 8 1 -R E V IS E D M A Y 1988 • Total Unadjusted Error . . . ± 0 . 7 5 LSB Max for A D C 0 8 0 8 and ± 1 . 2 5 LSB M ax for A 0C0809 • Resolution of 8 Bits

Contextual Info: L6 1 1 6 2K x 8 Static RAM Features Description_ □ 2K by 8 Static RAM with chip select powerdown, output enable The L6116 is a high-performance, lowpower CMOS static RAM. The storage circuitry is organized as 2048 words by 8 bits per word. The 8 Data

96-ball FBGA

Contextual Info: COVER PRELIMINARY DATA SHEET 1G bits DDR3L SDRAM EDJ1108EJBG 128M words x 8 bits EDJ1116EJBG (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization — 16M words × 8 bits × 8 banks (EDJ1108EJBG) — 8M words × 16 bits × 8 banks (EDJ1116EJBG)

Contextual Info: 144-pin, 2 Clock, 1-bank, based on 8 M x 8 Bit SDRAMs with SPD • DESCRIPTION The Fujitsu MB8508S064CH is a fully decoded, CMOS Synchronous Dynamic Random Access Memory SDRAM Module consisting of eight MB81F64842C devices which organized as two banks of 8 M x 8 bits and

EDE1108ACSE

Abstract: EDE1116ACSE
Contextual Info: DATA SHEET 1G bits DDR2 SDRAM EDE1104ACSE 256M words x 4 bits EDE1108ACSE (128M words × 8 bits) EDE1116ACSE (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization ⎯ 32M words × 4 bits × 8 banks (EDE1104ACSE) ⎯ 16M words × 8 bits × 8 banks (EDE1108ACSE)

TBP38L166

Contextual Info: TEXAS INSTR -CASIC/nEHORY} 70 D E I fl Tb lV aS 0036703 =1 | • -1 ^ 1, - 1 3 - 2 5 T B P 3 8 L 1 65, T B P 3 8 L1 6 6 , T B P 3 8 L 1 6 X 1 6 , 384-BIT 2048 WORDS BY 8 BITS LOW-POWER PROGRAMMABLE READ ONLY MEMORY WITH 3-STATE OUTPUTS D 2 9 0 9 . JA N U A R Y 1 9 8 5 -R E V IS E D JU LY 1 9 8 5

IDT7M145S

Abstract: IDT7M135 IDT7M145 IDT7M144S idt7m144
Contextual Info: 8K x 8 16K x 8 CMOS DUAL-PORT STATIC RAM MODULE SLAVE Integrated Device Technology, Inc. FEATURES: • High-density 64K/128K CMOS SLAVE Dual-Port static RAM modules • 16K x 8 (IDT7M 145) or 8K x 8 (IDT7M144) option • Easily expands data bus width to 16-or-more-bits when

Contextual Info: MITSUBISHI LSIs MH51208TNA-85L,- 10L,- 12L,- 15L/ MH51208TNA-85H,-10H,-12H,-15H 4 194304-BIT 5 2 4 2 8 8 -WORD BY 8-BIT CMOS STATIC RAM DESCRIPTION The M H 5 1 2 0 8 T N A is a 4 1 9 4 3 0 4 bits C M OS static R A M PIN CONFIGURATION (TOP VIEW) module organized as 524288-w ords by 8-bits. It consists

LH5116H

Contextual Info: LH5116/H C M O S 16K 2 K x 8 S tatic RAM FEATURES DESCRIPTION • 2,048 x 8 bit organization The LH5116/H are static RAMs organized a s 2 ,0 4 8 x 8 bits. It is fabricated using silicon-gate CMOS process technology. It features high speed access in read mode