8 BITS Search Results

AD9002

Abstract: AD9012 AD9048 AD9057 AD9058 AD9059 AD9066 AD9280 AD9281 AD9283
Contextual Info: A/D CONVERTERS: > 20MSPS, AC SPECS Con Full Power BW Mhz MODEL # Bits # A/D version Rate MSPS AD9066 6 1 60 AD9281 AD9280 AD9048 AD9058 AD9283 AD9057 AD9059 AD9012 AD9012 AD9012 AD9283 AD9283 AD9002 AD9054 AD9054 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 1 1 2 1 1 2

2444S

Abstract: S2465 AD7579 AD7580 AD7777 AD7778 AD7824 AD7825 AD7828 AD7829
Contextual Info: SUBSYSTEMS: DATA ACQUISTION MODEL # Bits Power Supply Requirements # Min +Icc CH +Vcc mA AD7824 AD7824 AD7828 AD7828 AD7825 AD7829 AD8401 AD8401 AD7777 8 8 8 8 8 8 with 1, 8 10 4 5 4 8 +5 8 4 +3 8 +3 8 bit D/A 4 +5V 4 +5 AD7778 10 8 +5 Power Down Iq uA Input

AD7721

Abstract: AD7575 AD7576 AD7776 AD7813 AD7819 AD7820 AD7821 AD7822 AD7892-1
Contextual Info: <1 MSPS, SAMPLING With T/H, Single Supply: Supply Requirements MODEL AD7575 AD7575 AD7576 AD7576 AD7813 AD7819 AD7820 AD7820 AD7821 AD7822 AD7813 AD7776 AD7892-1,2,3 # Bits 8 8 8 8 8 8 8 8 8 8 10 10 12 # CH +Vdd 1 1 1 1 1 1 1 1 1 1 1 1 1 +Idd Power Down Iq

AD73311

Abstract: AD73311L AD7339 AD7569 AD7669 AD7729 AD7774 AD7868 AD7869 AD8401
Contextual Info: A/D CONVERTERS: CODEC I/O PORTS MODEL # # # Bits CH's T/H # Dac's/ Bits AD7569 AD7569 AD7339 AD7669 8 8 8 8 1 1 1 1 1 1 S/D 1 1/8 1/8 4/8 2/8 AD7774 AD8401 8 8 2 4 2 1 3/8, 1/11 1 AD7729 AD7868 AD7868 12 12 12 2 1 1 AD7869 14 1 1 1/14 AD73311 AD73311L AD73322

Contextual Info: MITSUBISHI LSIs MH1M08TNA-85L,-10L,-12L,-15L/ MH1M08TNA-85H,-10H,-12H,-15H 8 3 8 8 6 0 8 -B IT 1 0 4 8 5 76-W ORD BY 8 -B IT C M 0 S STATIC RAM DESCRIPTION PIN C O N FIG U R A TIO N (TOP VIEW ) The M H 1 M 0 8 T N A is a 8 3 8 8 6 0 8 bits C M O S static RA M

Contextual Info: PRELIMINARY CMOS VIDEO RAM KM428C128 12 8 K X 8 Bit CMOS Video RAM FEATURES GENERAL DESCRIPTION • Dual port Architecture 128K x 8 bits RAM port 256 x 8 bits SAM port • Performance The Samsung K M 4 2 8 C 1 2 8 is a CMOS 1 2 8 K X 8 bit Dual Port DRAM. It consists ot a 1 2 8 K X 8 dynamic random

Contextual Info: MITSUBISHI LSIs MH1M08TNA-85L,-10L,-12L,-15L/ MH1M08TNA-85H,-10H,-12H,-15H 8 3 8 8 6 0 8 -B IT 1 0 4 8 5 7 6 -W 0 R D B Y 8-BIT CM OS STATIC RAM DESCRIPTION The M H 1 M 0 8 T N A is a 8 3 8 8 6 0 8 bits C M O S static RA M PIN C O N FIG U R ATIO N (TOP V IEW )

Contextual Info: PRELIMINARY CMOS VIDEO RAM KM428C128 1 2 8 K X 8 Bit CMOS Video RAM FEATURES GENERAL DESCRIPTION • Dual port Architecture 1 28K x 8 bits RAM port 256 x 8 bits SAM port • Performance The Samsung KM 428C128 is a CMOS 128 K X 8 bit Dual Port DRAM. It consists of a 1 2 8 K X 8 dynamic random

tca 780

Abstract: SOP32 DIP32 TA4F
Contextual Info: ¡Ordering number : ENì*< 5090A CMOS LSI No. 5090A LC3781OOPP, PM-10/LC3781OOPP, PM-20LV 8 MEG 1048576 words x 8 bits Mask ROM Internal Clocked Silicon Gate Preliminary Overview Package Dimensions The LC3 781 OOPP, PM-10 and LC378100PP, PM-20LV are 8 3 8 8 6 0 8 -b it M ask Program m able Read Only

Contextual Info: TMS28F008Axy TMS28F800Axy 8 3 8 8 6 0 8 BOOT-BLOCK FLASH MEMORIES _ * * 1048576 By 8 Bits 524288 By 16 Bits Array-Blocking Architecture - Two 8K-Byte Parameter Blocks - One 96K-Byte Main Block - Seven 128K-Byte Main Blocks - One 16K-Byte Protected Boot Block

Contextual Info: R8C/10 Group 1. Overview 1.3 Block Diagram Figure 1.1 shows this MCU block diagram. 8 8 I/O port Port P0 Port P1 1 5 2 Port P4 Port P3 Peripheral functions Timer Timer X 8 bits Timer Y (8 bits) Timer Z (8 bits) Timer C (16 bits) A-D converter (10 bits ✕ 8 channels)

TC518512FTL-70

Contextual Info: 5 2 4 ,2 8 8 W O R D S x 8 8 IT CMOS PSEUDO S T A T IC RAM PRELIMINARY D E S C R IP T IO N T he T C 5 1 8 5 1 2 P L F am ily is a 4M b it high speed CM OS Pseudo S tatic RAM organized as 5 2 4 ,2 8 8 words by 8 bits. T he T C 5 1 8 5 1 2 P L F am ily u tilizin g one transistor dynamic memory cell with CM OS

Contextual Info: TBP38S030, TBP38L030, TBP38SA030 TBP38S03X, TBP38L03X, TBP38SA03X 256-BIT 32 WORDS BY 8 BITS PROGRAMMABLE READ-ONLY MEMORIES D 2 8 5 2 .A U G U S T 1 9 8 4 -R E V IS E D JUNE 1 9 8 6 T B P 3 8 L 0 3 0 , T B P 3 8 S 0 3 0 . T B P 3 8 S A 0 3 0 . . . J OR N PACKAGE

Contextual Info: Renesas microcomputers M16C / 62P Group Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Diagram Figure 1.1.1 is a block diagram of the M16C/62P group. 8 8 8 Port P0 Port P1 8 Port P5 A-D converter System clock generator 10 bits X 8 channels XIN-XOUT

sm8500

Abstract: P317 100-PIN QFP100-P-1420 SM8504 SM8506 SM85CPU AD166
Contextual Info: PRODUCT INFORMATION SM8504/SM8506 8-Bit Single-Chip Microcomputers FEATURES • ROM capacity – 40,960 x 8-bits SM8504 – 61,440 × 8-bits (SM8506) • RAM capacity – 1,024 × 8-bits (SM8504) – 2,048 × 8-bits (SM8506) • Memory organization, it is possible to set the range of accessible

p088

Contextual Info: 8 8 Port P5 8 4 COM ✕ 24 SEG LCD drive control circuit (UART or Clock synchronous) Serial I/O2 (UART or Clock synchronous) Serial I/O1 Serial I/O 10-bit ✕ 8-channel A-D conversion 3 Port P6 (3) Watchdog timer PWM1 (10 bits) Timer 4 (8 bits) PWM0 (10 bits)

Contextual Info: UG38W324 8 8HSG 32M Bytes (8M x 32) DRAM 72Pin SODIMM based on 8M X 8 General Description Features The UG38W324(8)8HSG is a 8,388,8 bits by 32 SODIMM module. The UG38W324(8)8HSG is assembled using 4 pcs of 8M x 8 4K/8K refresh DRAMs in 32-pin TSOP package mounted on

Contextual Info: 1.5|i NON-VOLATILE LIBRARY RUGGED EEPROM* CELL NAME EEARRY TOTAL BITS* WRITE CYCLE DESCRIPTION 16 32 64 128 256 16 x 1 EEPROM ARRAY 32 x 1 EEPROM ARRAY 64 x 1, 16 x 4, 8 x 8 EEPROM ARRAY 1 2 8 x 1 ,3 2 x 4, 16 x 8, 8 x 1 6 EEPROM ARRAY 64 x 4, 32 x 8, 16 x 16 EEPROM ARRAY

UG38C3288HSG

Contextual Info: UG38C324 8 8HSG 32M Bytes (8M x 32) DRAM 72Pin SODIMM based on 8M X 8 General Description Features The UG38C324(8)8HSG is a 8,388,8 bits by 32 SODIMM module. The UG38C324(8)8HSG is assembled using 4 pcs of 8M x 8 4K/8K refresh DRAMs in 32-pin TSOP package mounted on

TC518128B

Abstract: TRANSISTOR BFW 11 pin diagram TC518128 TC518128bfl pin diagram of TRANSISTOR BFW 11 TC5181
Contextual Info: TOSHIBA T C 5 1 8 1 2 8 B P L /B S P L /B F L /B F W 1 V B F IL -7 0 /8 0 /1 0 T C 5 1 8 1 2 8 B P iy B S P L /B F V B F W L /B F H r 7 0 iy 8 0 L /1 0 L SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description The TC518128B is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518128B utilizes

Contextual Info: UG38E324 8 8HSG 32M Bytes (8M x 32) DRAM 72Pin SODIMM based on 8M X 8 General Description Features The UG38E324(8)8HSG is a 8,388,8 bits by 32 SODIMM module. The UG38E324(8)8HSG is assembled using 4 pcs of 8M x 8 4K/8K refresh DRAMs in 32-pin TSOP package mounted on

LB1616

Abstract: HN25088S HN25089S
Contextual Info: HN25088S, HN25089S — Preliminary— 1024-word x 8-bit Programmable Read Only Memories The H IT A C H I H N 2 5 0 8 8 S and H N 2 5 0 8 9 S are high speed electrically programmable, fully decoded T T L Bipolar 8 1 9 2 bit-read only memories organized as 1024 w ords by 8 bits with on-chip address

HMU 1

Contextual Info: ¡Ordering number : EN%; 5090A | CMOS LSI No. X 5090A SAXYO LC378100PP, PM-10/LC3781OOPP, PM-20LV 8 MEG 1048576 words x 8 bits Mask ROM Internal Clocked Silicon Gate Preliminary Overview Package Dimensions The LC3781 OOPP, PM-10 and LC378100PP, PM-20LV a re 8 3 8 8 6 0 8 -b it M ask P ro g ra m m a b le R ead O nly

Contextual Info: UG58W664 8 8HK(S)G 64M Bytes (8M x 64) DRAM 168Pin DIMM based on 8M x 8 General Description Features The UG58W664(8)8HK(S)G is a 8,388,8 bits by 64 EDO DRAM module. The UG58W664(8)8HK(S)G is assembled using 8 pcs of 8Mx8 4K/8K refresh DRAMs in a 32 pin 400