7C1049 Search Results

r32d

Abstract: CY7C1049 140C JESD22 CY7C1048
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97344 VERSION 1.0 March, 1998 R32D Technology - Metal 2 Hot Aluminum Cypress Semiconductor, Inc. R32D Technology - Hot Aluminum Metal 2 - Fab4 Device: 7C1049 7C1049A Package: SOJ QTP# 97344, V. 1.0 Page 2 of 7

Contextual Info: fax id: 1082 — — • PRELIMINARY 7C1049 5 1 2K x 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

Contextual Info: 7C1049BN 7C1049BN 512 K x 8 Static RAM Features Functional Description • High speed ❐ tAA = 17 ns ■ Low active power ❐ 1073 mW max. ■ Low CMOS standby power ❐ 2.75 mW (max.) ■ 2.0 V data retention (400 W at 2.0 V retention) The 7C1049BN is a high-performance CMOS static RAM

Contextual Info: 7C1049BN 512 K x 8 Static RAM 512 K × 8 Static RAM Features Functional Description • High speed ❐ tAA = 17 ns The 7C1049BN is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE , an active LOW

CY7C1049V33

Abstract: CY7C1049V33-20VI CY7C1049V33-25VI
Contextual Info: 049V33 7C1049V33 512K x 8 Static RAM Features • High speed — tAA = 15 ns • Low active power — 504 mW max. • Low CMOS standby power (Commercial L version) — 1.8 mW (max.) • 2.0V Data Retention (660 µW at 2.0V retention) • Automatic power-down when deselected

CY7C1049B-20VI

Abstract: CY7C1049B-15VC CY7C1049B-25VI CY7C1049B CY7C1049B-12VC CY7C1049B-20
Contextual Info: 049B 7C1049B 512K x 8 Static RAM Features is provided by an active LOW Chip Enable CE , an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0

Contextual Info: fax id: 1082 W CYPRESS PRELIMINARY 512Kx 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­ able (WE) inputs LOW. Data on the eight I/O pins (l/O0 through

EPM5128LC

Abstract: IDT CYPRESS CROSS REFERENCE clocks epm5064lc-1 EPM5128LC-1 EPM5064LC EPM5128LC-2 EPM5128GI EPM5128JC-1 8464c 5962-8871309
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2148-35C CY21L48-35C CY7C168A-35C CY7C168A-25C 5962-8871309XX 5962-89839112X CY2148-35C CY7C148-35C CY7C168A-45M CY7C168A-35M+ 5962-8871310RX 5962-8983913RX CY2148-35M CY7C148-35M CY7C169A-35C

CY7C1049V33-20VI

Abstract: CY7C1049V33-25VI CY7C1049V33 7C1049 CY7C1049V33-15VC
Contextual Info: 3 7C1049V33 512K x 8 Static RAM Features • High speed — tAA = 15 ns • Low active power — 504 mW max. • Low CMOS standby power (Commercial L version) — 1.8 mW (max.) • 2.0V Data Retention (660 µW at 2.0V retention) • Automatic power-down when deselected

Contextual Info: fax id: 1082 W CYPRESS PRELIMINARY 7C1049 5 1 2 K x 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­

CY7C1049

Abstract: CY7C1049-15VC CY7C1049L-15VC
Contextual Info: fax id: 1082 PRELIMINARY 7C1049 512K x 8 Static RAM Features • High speed — tAA = 15 ns • Low active power — 1210 mW max. • Low CMOS standby power (Commercial L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

verilog for SRAM 512k word 16bit

Abstract: CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip
Contextual Info: Product Selector Guide Static RAMs Organization/Density Density X1 X4 4K X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195 7C199 7C1399/V 62256/V 62256V25 62256V18

CY7C1049-20

Contextual Info: fax id: 1082 C Y 7C 1049 CY7C 1049L 512K x 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­ able (WE) inputs LOW. Data on the eight I/O pins (l/O0 through

OW14

Contextual Info: fax id: 1082 7C1049 512K x 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (GE) and write en­ able (WE) inputs LOW. Data on the eight I/O pins (l/O0 through

2M X 32 Bits 72-Pin Flash SO-DIMM

Abstract: AN2131QC Triton P54C SO-DIMM 72pin 32bit 5V 2M AN2131-DK001 AN2131SC vhdl code for pipelined matrix multiplication VIC068A user guide parallel interface ts vhdl 7C037
Contextual Info: GO TO WEB MAIN INDEX 3URGXFW 6HOHFWRU *XLGH Static RAMs Organization/Density Overview Density X1 X4 X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 4 Kb 16 Kb 7C167A 7C168A 7C128A 6116 64 Kb to 72 Kb 7C187 7C164 7C166 7C185 6264 7C182 256 Kb to 288 Kb 7C197 7C194

CY7C1049BN-17VXC

Abstract: CY7C1049BN CY7C1049BNL-17VC CY7C1049BN-15VI CY7C1049BN-20VXI CY7C1049BN-15VX
Contextual Info: 7C1049BN 7C1049BN 512K x 8 Static RAM Functional Description[1] Features • High speed — tAA = 12 ns • Low active power — 1320 mW max. • Low CMOS standby power (Commercial L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention)

CY7C1041BV33

Abstract: CY7C1046BV33 CY7C1049BV33
Contextual Info: Cypress Semiconductor Product Qualification Report QTP# 000305 VERSION 1.0 March, 2000 4 Meg Asynchronous SRAM R52D-3 Technology at Fab 4 CY7C1041BV33 256K x 16 Static RAM CY7C1046BV33 1M x 4 Static RAM 7C1049BV33 512K x 8 Static RAM CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:

CY7C1049-17VC

Abstract: t 1049 CY7C1049 CY7C1049-15VC 7C1049-20
Contextual Info: fax id: 1082 1CY 7C10 49 7C1049 7C1049L PRELIMINARY 512K x 8 Static RAM Features • High speed — tAA = 17 ns • Low active power — 1073 mW max. • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention)

CY7C1049V33

Contextual Info: 7C1049V33 CYPRESS_ 512K x 8 Static RAM Features sion is provided by an active LOW Chip Enable CE , an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (l/O0

ZL5.6

Abstract: H1311 soj 36 CY7C1049
Contextual Info: fax id: 1082 ; ; ; -Hi ' .üÉÉÉÉÉÉÉÉÉÉiüüiüHjjju'.' ; : ; IS. . : : : : : : ; ; ; ; : ; ;' : : : 7C1049 P R E L IM IN A R Y •rriM U M iM iiiu m m r t V - § « < !N : 5 1 2 K x 8 Static RAM Features is provided by an active LOW chip enable CE , an active LOW

CY7C1049V33

Abstract: CY7C1049V33-15VC CY7C1049V33L-15VC CY7C1049V33-20VC 7C1049V33-15
Contextual Info: fax id: 1096 33 PRELIMINARY 7C1049V33 512K x 8 Static RAM Features sion is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0

CY7C1049D

Abstract: V36 Package
Contextual Info: PRELIMINARY 7C1049D 4-Mbit 512K x 8 Static RAM Functional Description[1] Features • Pin- and function-compatible with 7C1049B The 7C1049D is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an

1049B

Abstract: CY7C1049B CY7C1049B-20VI CY7C1049B25VC
Contextual Info: 7C1049B 512K x 8 Static RAM Features is provided by an active LOW Chip Enable CE , an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0