7777X Search Results

47c820

Contextual Info: TOSHIBA UC/UP 54E J> • TORTEMT 0 0 n 4 7 Q 524 « T O S S ' TOSHIBA TMP47P820 CMOS 4-BIT MICROCONTROLLER TMP47P820F The 47P820 is the OTP microcontroller with 64kbits PROM. For program operation, the programming is achieved by using with EPROM programmer (TMM2764AD type) and adapter socket (BM 1 112).

Contextual Info: | CMOS Bus-Matching SyncFlFO 256 x 36, 512 x 36,1,024 x 36 dt PRELIMINARY ¡DT723633 IDT723643 Integrated D ev ic e Techno logy, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

HD44238

Abstract: DS2130 DS2130Q DSZ130Q HD44238C LM130
Contextual Info: DS2130Q DS2130Q DALLAS SEMICONDUCTOR Voice Messaging Processor PIN ASSIGNMENT FEATURES • Per-channel voice messaging processor for digitized voice storage and retrieval • High fidelity speech recording and playback at 8,12, 16, 24 and 32 Kbits/sec • Integral DTMFtransceiverfor remote touch-tone con­

DS2165Q

Contextual Info: D S 2165/D S2165Q DALLAS SEMICONDUCTOR D S 2 1 6 5 /D S 2 1 6 5 Q 16/24/32Kbps ADPCM Processor PIN ASSIGNMENT FEATURES • Compresses/expands 64Kbps PCM voice to/from either 32Kbps, 24Kbps, or 16Kbps • Dual, fully independent channel architecture; device

Contextual Info: HM5216808C Series HM5216408C Series 1,048,576-word x 8-bit x 2-bank Synchronous Dynamic RAM SSTL-3 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM (SSTL-3) HITACHI ADE-203-617 (Z) Preliminary Rev. 0.0 Jul. 10, 1996 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216808C Series,

9704CG3

Contextual Info: F*B 3 892 9704 D ata Compression Coprocessor STAC D ata Sheet • Product Description I Features The Stac 9704 is a high-performance data compres­ sion coprocessor for use in data storage and trans­ mission applications. Using a compression algorithm optimized for high-speed file streams, the

7777X

Contextual Info: TOX 9003 iT T " ^ f if w # i Gallium Aluminum Arsenide Light Emitting Diode T e xa s O p to e le c tr o n ic s , in c . DESCRIPTION FEATURES High radiance GaAIAs IR LED optimized for coupling to a variety of fibers. The unique LED chip design combines high power coupling with

SBP9989

Abstract: 9960 SBP9960 sbp 11 SBP 9960
Contextual Info: SBP 9960 SBP 9960 PROGRAMMABLE CRU I/O EXPANDER 1.0 INTRODUCTION 1.1 GENERAL DESCRIPTION The SBP 9960 Programmable CRU I/O Expander is a ruggedized monolithic software-configurable input/output device fabricated with oxide separated Integrated Injection Logic |2 l technology. The

DS1231

Abstract: DS2165 DS2165QL DS2167 DS2165Q
Contextual Info: D S 2 16 5/D S 2 16 5 Q D A L L A S s e m ic o n d u c t o r D S 2 1 6 5 /D S 2 1 6 5 Q ^ 6/24/32Kbps AD PCM Processor FEATURES • C om presses/expands 64Kbps PCM voice to/from either 32Kbps, 24Kbps, or 16Kbps • Dual, fully independent channel architecture; device

B1581

Abstract: B1379 bl238
Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 • • • • • • • • • • FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident sim ultaneous reading and writing of data on a single clock edge is perm itted

Contextual Info: CO M PO NENTS _ ; Impervious lead free vitreous enamel coating High purity ceramic substrate Based on thirteen tube sizes Can be supplied with fixed, adjustable, tapped or low inductance winding. Seven termination styles with choice of mounting arrangments

Contextual Info: □ ANALOG DEVICES FEATURES Complete Monolithic 14-Bit ADC 2s Complement Coding Parallel, Byte and Serial Digital Interface 80 dB S N R at 10 kHz Input Frequency 57 ns Data Access Time Low Pow er-50 m W typ 83 kSPS Throughput Rate 16-Lead SO IC AD7872 lc2mos

Contextual Info: bq4016/bq4016Y U N IT R O D E Features >• D ata retention in the absence of power ► Automatic write-protection dur­ ing power-up/power-down cycles >• Conventional SRAM operation; unlimited write cycles >- 10-year minimum data retention in absence of power

Contextual Info: HB526C272EN-10IN, HB526C472EN -10IN 1.048.576-word x 72-bit x 2-bank Synchronous Dynamic RAM Module 1.048.576-word x 72-bit x 4-bank Synchronous Dynamic RAM Module HITACHI ADE-203-693C Z Rev. 3.0 May. 15,1997 Description The HB526C272EN, HB526C472EN belong to 8-byte DIMM (Dual In-line Memory Module) family, and

mb86901

Contextual Info: F U J IT S U High Performance 32-Bit RISC Processor SPARC FEATURES • Architecture supports scalability towards faster technologies • Address presentation which supports highperformance cache • 15 times V A X ™ 11/780 equivalent MIPS typical performance

DS2165Q

Contextual Info: “ m m c o m m c tm DS2165/DS2165Q 16/24/32kpbs ADPCM Processor PIN ASSIGNMENT FEATURES • Compresses/expands 64 kbps PCM voice to/from either 32 kbps, 24 kbps, or 16 kbps ■ Dual, fully independent channel architecture; device can be programmed to perform either:

Contextual Info: TOSHIBA TLCS-470A Series TMP47P1620V CMOS 4-Bit Microcontroller PROM. For program operation, the programming is achieved by using with EPROM programmer TMM27128AD type and adapter socket. AC/DC characteristics are equivalent to Mask-pro­ grammed ROM device.

Contextual Info: ADE-203-186A Z i HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM H IT A C H I All inputs and outputs are referred to the rising edge of the clock input. The HMS241605 is offered in 2 banks for improved performance. 3.3 V Power supply

08216

Abstract: HD44238C DS1231 DS2164Q DS2165 ia4a5
Contextual Info: D S 2164Q DALLAS SEMICONDUCTOR FEATURES DS2164Q G.726 ADPCM Processor PIN ASSIGNMENT • C om presses/expands 64Kbps PCM voice to/from eith er32 K b ps, 24Kbps, or 16Kbps as per the CCITT/ ITU G.726 specification NC [ • Dual, fully independent channel architecture; device

ir tk 2238

Abstract: IT191 CA10 V54C365804VC tk 2238 7777777Z
Contextual Info: M O S E L V IT E L IC V54C365804VC HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT8MX8SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143MHz 133MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3 ) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3

mhtl

Contextual Info: HM5221605 Series 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-199A Z Rev. 1.0 Jun. 22,1995 Description All inputs and outputs are referred to the rising edge of the clock input. The HM 5221605 is offered in 2 banks for improved performance.

Contextual Info: TOSHIBA TLCS-470A Series TMP47P1670V CMOS 4-Bit Microcontroller EPROM. For program operation, the programming is achieved by using with EPROM programmer TMM27128AD type and adapter socket (BM1133). TMP47P1670VN The function of this device is exactly same as the

Contextual Info: TOSHIBA TMP87PP71 UNDER DEVELOPMENT CMOS 8-BIT MICROCONTROLLER TMP87PP71F The 87PP71 is a One-Tim e PROM m icrocontroller with low -pow er 384K bits 48K bytes electrically programmable read only memory for the 87CM71/N71/P71 system evaluation. The 87PP71 is pin compatible

v52c4258

Contextual Info: M O S E L VTTEUC V52C4258 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512 X 4 SAM HIGH PERFORMANCE V52C4258 Max. RAS Access Time, I rac 60 70 80 10 60 ns 70 ns 80 ns 100 ns 25 ns Max. CAS Access Time, Ocac ) 15 ns 20 ns 25 ns Max. Column Address Access Time, Paa )