77777A Search Results

427E-8

Abstract: ZN427E-8
Contextual Info: ZE TE X INC =iS D • = ^ 70570 OODSTbT 4 95D 0 5 9 6 9 Microprocessor compatible 8-bit successive approximation A-D converter * S 7 ' / o ^ o 8 ' ZN427E-8 ZN427J-8 FEATURES DESCRIPTION • The ZN427 is a 8 -bit successive approximation converter with three-state outputs to permit

BI71

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for

j477

Abstract: V54C365164VC
Contextual Info: M O S E L V IT E L IC V54C365164VC HIGH PERFORMANCE 143/133/125 MHz 3.3 V 0 L T 4 M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143 MHz 133 MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3

514256-10

Abstract: HM514256 hitachi HM514256
Contextual Info: HM514256 Series 262144-word x 4-bit CMOS Dynamic RAM T h e H itachi H M 5 1 4 2 5 6 Series is a C M O S d y n a m ic R A M o r ­ ganized 2 6 2 1 4 4 -w o r d x 4-bit. H M 514256P Series H M 5 1 4 2 5 6 has realized higher density, higher perform ance and variou s fu n c tio n s b y e m p lo y in g

Contextual Info: M OSEL VITELIC V54C316802VA HIGH PERFORMANCE 3.3 VOLT2M X 8 SYNCHRONOUS DRAM 2 BANKS X 1MBit X 8 CAS Latency = 3 PRELIMINARY 8 10 12 System Frequency fCK 125 MHz 100 MHz 83 MHz Clock Cycle Tim e (tcK 3 ) 8 ns 10 ns 12 ns Clock Access Tim e (tAC3) 7 ns 8 ns

6502 microprocessor

Abstract: plessey cla 3000 crompton K-50-50 ferranti ztx SP92701 draw pin configuration of ic 7404 SP9754
Contextual Info: DATA CONVERTERS & Voltage References IC Handbook APLE SSE Y Sem iconductors Foreword The collective description of Data Conversion covers a vast range of applications which is limited only by the imagination of today’s system designers. Traditionally the name of Plessey

R40 AH

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are

NEC 421000

Abstract: TTL 7404 421000 60 PD71088 7404 uPD421000 LS112 sn 7404 n ic diagram LM 7404 ic 421000
Contextual Info: J V f« L Z NEC Electronics Inc. APPLICA TIO N NOTE 5 3 //P D 4 2 10 00 /y u P D 421 00 1/yu P D 4 21 002 1 - m e g a b it d y n a m ic r a m s Description NEC’s //PD421000, juPD421001, and ¿IPD421002 are 1-m egabit dynam ic RAMs DRAMs m anufactured with

64kx1

Abstract: IDT6167 IDT7M164L100 IDT7M164L60 IDT7M164L70 IDT7M164L85 16kx1 static ram
Contextual Info: i ö4K 64K x i CM OS STATIC RAMPAK Integrated Device Technology. Inc IDT7M164 64K RAMPAK FEATURES: • 65,536x1 b it s ta tic R A M m o d u le c o m p le te w ith d e c o d e r a n d d e c o u p lin g c a p a c ito r • H ig h -s p e e d 60 (c o m m e rc ia l o n ly )/7 0 /8 5 /1 0 0 n s (e q u a l

Contextual Info: HM5241605C Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A D E - 2 0 3 - 1 8 6 A Z R e v . 1 .0 M ay. 22, 1996 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2

HM5241

Abstract: HM5241605CTT15
Contextual Info: HM5241605C Series Preliminary 131,072-w ord x 16-bit x 2-bank Synchronous Dynam ic RAM H IT A C A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2 banks for improved performance. Features • 3.3 V Power supply

Contextual Info: HM5221605 Series Preliminary 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clo ck input. The HM5221605 is offered in 2 banks for improved performance. Features Rev. 0.1 Sep. 22,1994

77777AV

Abstract: R7F7
Contextual Info: H M 5 2 4 1 6 5 - 1 Preliminary 2 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605 is offered in 2 banks for improved performance. Features m Rev. 0.0 Jan. 27,1995

Contextual Info: h a r r is H D -6 4 0 8 Ê M S E M I C O N D U C T O R CMOS Asynchronous Serial Manchester Adapter ASMA March 1997 Features Description • Low Bit Error Rate The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder for creating a very high speed asynchronous serial data bus.

Contextual Info: HM5216326 Serie 16M LVTTL interface SGRAM 2-Mword x 32-bit 125 MHz/100 MHz/83 MHz HITACHI ADE-203-678B (Z) Preliminary, Rev. 0.3 Jan. 14,1998 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5216326 provides 2

Contextual Info: HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RA M HITACHI ADE-203-280 A (Z) Preliminary Rev. 0.1 Oct. 20,1995 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.

Contextual Info: Æ3RBCT».*nstasdi:zr*i- re t •c -'t t *-. I LOC Q5ST:J drawing m ade in th ir d a n g l e p r o je c t io n rb REVISIONS /F ZONE LTR DATE APPROVED DESCRIPTION E ’ P£^ ÄD-5D84 2*/-9/ W y l/ F REV PER Ô S Î Û - 0 / 4 & " £ ¿3 SAS Copyright 1975-22

NEC 2501 DJ 423

Abstract: "lcd 2 8" PD7533 558 timer NEC disk controller 75336GC PIN DIAGRAM OF 7 segment display LT 542 77777AV upd75390
Contextual Info: USER’S MANUAL NEC M\ 4-B IT SINGLE-CHIP MICROCOMPUTER aPD75336 ^PD75P338 • b457525 00*14044 b6T NEC Corporation 1991 n The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without th e prior w ritten

Xm m mx

Contextual Info: M O S E L V IT E L IC V54C328804VC HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 PRELIMINARY 7 75 8 System Frequency fCK 143 MHz 133 MHz 125 MHz Clock Cycle Time (tcK3 ) 7 ns 7.5 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3

MN5280

Abstract: MN5282 MN5284
Contextual Info: MN5280 MN5282 / K K f f M ic r o N e tw o r k s a d iv is i o n o r u n « t m o m c o r p o ra tio n DIP-PACKAGED 16-Bit A/D C O N V E R T E R S DESCRIPTION FEATURES • Small 32-Pin DIP • Internal Clock and Reference • Maximum Conversion Time: MN5280 100/tsec

HM53461ZP-12

Abstract: HM53461ZP-10 HM53461P-10 HM53461P-12 hm53461-12 HM53461 HM53461P-15 HM53461ZP-15 Hitachi Scans-001
Contextual Info: HM53461 Series 65,536-word x 4-bit Multiport CMOS Video RAM • DESCRIPTION HM 53461P Series The HM53461 is a 262,144-bit multiport memory equipped with a 64k-word x 4-bit Dynamic RAM port and a 256-word x 4-bit Serial Access Memory SAM port. The SAM port is connected to an internal 1,024-bit data register through a 256-word

L0821

Abstract: SAFT MP DB8L wa8k catu IR71 b5757 256X16 TSOP50 acro eng
Contextual Info: KNo N & 5 7 5 7 /V O ,* 5 7 5 7 - J . - Z 02207 C M O S LSI LC382161AT-12/15 2m T655369-Vx 16t'jl>x2AV#i/2 ptXDRAIi l A*, jfc J ^ c jr «1« LC3B2161 A T ti, 65630 7 - H X lfl ^ -y V x 2A V ? to Ä « 3.3V # - « ¡MK i f tz ¿ DRAM)’0 * . 6 . M )i2CM 08:um ¿

Contextual Info: M O S E L V IT E L IC V54C365404VB HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4 PRELIMINARY 7 75 8P C 8 S y s te m F re q u e n c y fCK 143 M H z 133 M H z 125 M H z 125 M H z C lo c k C y c le T im e (tcK 3 ) 7 ns

Contextual Info: HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-280A Z Rev. 1.0 Dec. 20, 1996 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.