74LVX00 Search Results

74LVX00

Abstract: 74LVX00M 74LVX00MTC 74LVX00SJ LVX00 M14A M14D MTC14
Contextual Info: 74LVX00 Low Voltage Quad 2-Input NAND Gate Features General Description • Input voltage level translation from 5V to 3V The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

74LVX00

Contextual Info: 74LVX00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE . HIGH SPEED: tpD =4.1 ns TYP. at Vcc = 3.3V . INPUT VOLTAGE LEVEL: V il = 0.8V, V ih = 2V at Vcc = 3V . LOW POWER DISSIPATION: Icc = 2 |oA (MAX.) at T a = 25 °C . LOW NOISE: V o l p = 0 .3 V (TYP.) at V c c = 3 .3 V

74LVX00

Contextual Info: S E M [CONDUCTOR TM 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVXOO contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V sys­ tems to 3V systems. • Input voltage level translation from 5V to 3V

Contextual Info: Section 8 LV X Family * Section 8 Contents LVX Family Features. 74LVX00 Low Voltage Quad 2-Input NAND G a t e .

74LVX00

Abstract: 74LVX00M 74LVX00T TSSOP14
Contextual Info: 74LVX00 LOW VOLTAGE CM O S QUAD 2-IN P U T NAND GATE . . . . . . HIGH SPEED: tpD =4.1 ns TYP. at V cc = 3.3V INPUT VOLTAGE LEVEL: V il = 0.8V, V ih = 2V at V cc = 3 V LOW POWER DISSIPATION: Icc = 2 |uA (MAX.) at T a = 25 °C LOW NOISE: Volp = 0.3 V (TYP.) at Vcc = 3.3V

74LVX00

Abstract: 74LVX00M 74LVX00T TSSOP14
Contextual Info: 74LVX00  LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.1 ns TYP. at VCC = 3.3V INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V

truth table NAND gate 74

Abstract: 74LVX00 74LVX00M 74LVX00MTR 74LVX00TTR TSSOP14
Contextual Info: 74LVX00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVX00SJ

Abstract: LVX00 M14A M14D MTC14 74LVX00 74LVX00M 74LVX00MTC
Contextual Info: 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. n Input voltage level translation from 5V to 3V n Ideal for low power/low noise 3.3V applications

LVX00

Abstract: 74LVX00 74LVX00M 74LVX00MTC 74LVX00SJ M14A M14D MTC14
Contextual Info: Revised September 2003 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. • Input voltage level translation from 5V to 3V

74LVX00

Abstract: 74LVX00M 74LVX00MTC 74LVX00MTCX 74LVX00MX 74LVX00SJ 74LVX00SJX M14A M14D
Contextual Info: LVXOO National Semiconductor 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVXOO contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V sys­ tems to 3V systems. • Input voltage level translation from 5V to 3V

74LVX00

Abstract: 74LVX00M 74LVX00MTC 74LVX00MTCX 74LVX00MX 74LVX00SJ 74LVX00SJX LVX00 M14A M14D
Contextual Info: 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVX00 contains four 2-input NAND gates The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems Y Y Y Y Logic Symbol Input voltage level translation from 5V to 3V

BT 151 PIN DIAGRAM

Abstract: 74LVX00 74LVX00M 74LVX00MTC 74LVX00SJ M14A M14D MTC14 B738 772 soic 8
Contextual Info: S E M IC O N D U C T O R tm 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVXOO contains four 2-input N AND gates. The inputs to l­ erate voltages up to 7V allowing th e interface of 5V system s to 3 V system s. • Input voltage level translation from 5V to 3V

d flip flop

Abstract: quad 2-input nand schmitt trigger 74LVX00 74LVX02 74LVX04 74LVX08 74LVX112 74LVX125 74LVX132 74LVX14
Contextual Info: Logic Products by Family LVX Low Voltage Products Logic Product Function Product Description Package Voltage Node 74LVX00 Gate Low Voltage Quad 2-Input NAND Gate SOIC SOP TSSOP 2.7 3.3 74LVX02 Gate Low Voltage Quad 2-Input NOR Gate SOIC SOP TSSOP 2.7 3.3

74LVX00

Abstract: 74LVX00M 74LVX00MTR 74LVX00TTR TSSOP14
Contextual Info: 74LVX00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVX00

Abstract: 74LVX00M 74LVX00MTC 74LVX00MTCX 74LVX00MX 74LVX00SJ LVX00 M14A M14D MTC14
Contextual Info: Revised February 2005 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. • Input voltage level translation from 5V to 3V

74LVX00

Contextual Info: 74LVX00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE . HIGH SPEED: tpD =4.1 ns TYP. at Vcc = 3.3V . INPUT VOLTAGE LEVEL: V il = 0.8V, V ih = 2V at Vcc = 3V . LOW POWER DISSIPATION: Icc = 2 |oA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0.3 V (TYP.) at Vcc = 3.3V

Contextual Info: S E M IC O N D U C T O R 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVXOO contains lour 2-input NAND gates. The inputs tol­ erate voltages up to 7V allowing the interface of 5V systems to 3V systems. • Input voltage level translation trom 5V to 3V

74LVX00

Abstract: 74LVX00M 74LVX00T TSSOP14
Contextual Info: 74LVX00  LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.1 ns TYP. at VCC = 3.3V INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V

74LVX00

Abstract: 74LVX00TTR 74LVX00MTR TSSOP14
Contextual Info: 74LVX00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

Contextual Info: 74LVX00 Low Voltage Quad 2-Input NAND Gate Features General Description • Input voltage level translation from 5V to 3V The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

74LVX132

Abstract: 74LVX00 74LVX132M 74LVX132MTR 74LVX132TTR TSSOP14
Contextual Info: 74LVX132 LOW VOLTAGE CMOS QUAD 2-INPUT SCHMITT NAND GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 5.9ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C TYPICAL HYSTERESIS : 0.7V at VCC = 3.3V

TTL 74-series IC LIST

Abstract: 74 Series Logic ICs TTL 74-series IC PO74G74 PO74G04 list cmos ics 49fct32805 49FCT3807 Potato Semiconductor 49FCT3805
Contextual Info: 04/18/07 Pin to Pin & Package to Package Compatible IC List Standard 1.65V -3.6 V TTL / CMOS Clock Buffer PotatoSemi PO49FCT3802A 1GHz 1 to 5 PO49FCT3803B 700MHz 1 to 7 PO49FCT3804 800MHz 2X1 to 4 PO49FCT3805B 800MHz 2X1 to 5 PO49FCT3806 750MHz 2X1 to 5 PO49FCT3807B

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

74LVT JK Flip Flop

Abstract: led driver SOT23 6pin lcx244 MOTOROLA lcx 4245 LCX244 quad single supply 50 Ohm Line Drivers diode sj Fairchild Power Switch package to 220 p5 MAX 16841 On semiconductor LCX 574 PA
Contextual Info: 1 Chapter 1 Introduction to Low-Voltage Logic Chapter C R O S S V O L T Parts & Availability 17 Packaging Options 37 Low-Voltage Logic Cross Reference 49 Glossary 57 Fairchild Low-Voltage Logic Reference Guide Chapter Chapter Glossary  Introduction to Low-Voltage Logic