74LCX11 Search Results

Contextual Info: Revised February 2005 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The LCX11 is a triple 3-input AND gate with buffered outputs. LCX devices are designed for low voltage 2.5V or 3.3V operation with the added capability of interfacing to a

Contextual Info: 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs Features General Description • 5V tolerant inputs The LCX11 is a triple 3-input AND gate with buffered outputs. LCX devices are designed for low voltage 2.5V or 3.3V operation with the added capability of interfacing to a 5V signal environment.

74LCX11

Abstract: 74LCX11M 74LCX11SJ M14A M14D MTC14 LCX11 FAIRCHILD
Contextual Info: s e m ic o n d u c t o r Revised M arch 1999 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features T he LCX11 is a triple 3-inpu1 AND gate with buffered o ut­ puts. LCX devices are designed fo r low voltage 2.5V or

Contextual Info: S E M I C O N D U C T O R Revised A ugust 1998 TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has indejDendent J, K, PRESET, CLEAR, and C LO C K inputs with Q,

74LCX112

Abstract: 74LCX112M 74LCX112MX 74LCX112SJ M16A
Contextual Info: 74LCX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX112 are dual J-K flip-flops. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs Q, Q outputs. These devices are edge sensitive and change state

Contextual Info: Revised August 1998 SE M IC O N D U C TO R TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has inde£endent J, K, PRESET, CLEAR, and CLOCK inputs with Q,

lcx11

Contextual Info: ADVANCE INFORMATION LCX11 iß National Semiconductor 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The 74LCX11 is a triple 3-input AND gate with buffered out­ puts. LCX devices are designed for low voltage 3.3V oper­

LCX11

Contextual Info: ADVANCE INFORMATION Semiconductor 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The 74LCX11 is a triple 3-input AND gate with buffered out­ puts. LCX devices are designed for low voltage 3.3V oper­ ation with the added capability of interfacing to a 5V signal

diode M160

Abstract: 74LCX112 74LCX112M 74LCX112MTC 74LCX112MTCX 74LCX112MX 74LCX112SJ 74LCX112SJX M16A
Contextual Info: PRELIMINARY Semiconductor LCX112 & National 74LCX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX112 are dual J-K flip-flops. Each flip-flop has in­ dependent J, K, PRESET, CLEAR, and CLOCK inputs Q, Q

Contextual Info: Revised March 1999 SEMICONDUCTOR TM 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The LCX11 is a triple 3-input AND gate w ith buffered o ut­ puts. LCX devices are designed fo r low voltage 2.5V or 3.3V operation w ith the added capability of interfacing to a

Contextual Info: EMICONDUCTQRr 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The LCX11 is a triple 3-input AND gate with buffered outputs. LCX devices are designed for low voltage 3.3V operation with the added capability of interfacing to a 5V signal envi­

Contextual Info: Revised June 1998 S E M I C O N D U C T O R TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has indepen­ dent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q out­

74LCX11M

Abstract: 74LCX11MTC 74LCX11SJ M14A M14D MTC14 74LCX11
Contextual Info: Revised March 1999 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The LCX11 is a triple 3-input AND gate with buffered outputs. LCX devices are designed for low voltage 2.5V or 3.3V operation with the added capability of interfacing to a

Contextual Info: Revised June 2005 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The LCX11 is a triple 3-input AND gate with buffered outputs. LCX devices are designed for low voltage 2.5V or 3.3V operation with the added capability of interfacing to a

Contextual Info: Revised February 2001 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change

LCX112

Abstract: MTC16 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D
Contextual Info: Revised February 2001 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change

LCX112

Contextual Info: LCX112 tß National ADVANCE INFORMATION Semiconductor 74LCX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX112 are dual J-K flip-flops. Each flip-flop has In­ dependent J, K, PRESET, CLEAR, and CLOCK inputs Q, <3

74LCX112

Abstract: 74LCX112M 74LCX112MTC 74LCX112SJ LCX112 M16A M16D MTC16
Contextual Info: Revised March 1999 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change

Contextual Info: S E M I C O N D U C T O R Revised M arch 1999 TM 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The LCX11 is a triple 3-input AND gate w ith buffered o ut­ puts. LCX devices are designed fo r low voltage 2.5V or

74LCX112

Abstract: 74LCX112M 74LCX112MTC 74LCX112SJ LCX112 M16A M16D MTC16
Contextual Info: S E M IC O N D U C T O R Revised March 1999 TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features T he LCX112 is a dual J-K flip-flop. Each flip-flop has inde­ pendent J, K, PRESET, C LEAR, and C LO C K inputs with Q,

74LCX11

Abstract: 74LCX11M 74LCX11SJ M14A M14D MTC14
Contextual Info: s e m ic o n d u c t o r Revised M arch 1999 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features T he LCX11 is a triple 3-inpu1 AND gate with buffered o ut­ puts. LCX devices are designed fo r low voltage 2.5V or

"J-K Flip flops"

Abstract: 74LCX112MTC 74LCX112 74LCX112M 74LCX112MTCX 74LCX112MX 74LCX112SJ 74LCX112SJX C1996 M16D
Contextual Info: December 1996 74LCX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX112 are dual J-K flip-flops Each flip-flop has independent J K PRESET CLEAR and CLOCK inputs Q Q outputs These devices are edge sensitive and change state

74LCX11

Abstract: 74LCX11BQX 74LCX11M 74LCX11MTC 74LCX11SJ M14A M14D MTC14
Contextual Info: 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs Features General Description • 5V tolerant inputs The LCX11 is a triple 3-input AND gate with buffered outputs. LCX devices are designed for low voltage 2.5V or 3.3V operation with the added capability of interfacing to a 5V signal environment.

74LCX11

Abstract: 74LCX11M 74LCX11MTC 74LCX11SJ M14A M14D MTC14
Contextual Info: Revised January 2001 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs General Description Features The LCX11 is a triple 3-input AND gate with buffered outputs. LCX devices are designed for low voltage 2.5V or 3.3V operation with the added capability of interfacing to a