74LS14 Search Results

DN74LS145

Contextual Info: LS TTL DN74LS Series 74LS145 74LS145 iv ^ L S ^ BCD to Decimal Decoders / Drivers P-2 • Description DN 74LS145 is a BCD to decim al decoder/ driver w ith open collector o u tp u ts. ■ Features • • • • Large o u tp u t cu rrent I o l ^ 80m A m axim um )

74LS14PC

Abstract: 7414PC PIN OUT 74LS14 pin diagram of 7414 74LS14 5414DM schmitt trigger 7414 74LS14DC 7414DC 7414
Contextual Info: 14 CON NECTIO N DIAG RAM PINO UT A 54/7414 r '''54LS/74LS14 ¿v/ ' 7/ HEX SC HM ITT TRIGGER INVERTER I ORDERING CODE: See Section 9 PIN PKGS OUT Plastic DIP P A Ceramic DIP (D) A COMMERCIAL GRADE V cc = +5.0 V ±5%, T a = 0 °C to +70° C MILITARY GRADE

Contextual Info: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which performs the logic INVERT function. Each in­ put has hysteresis which increases the noise im­ munity and transforms a slowly changing input signal

Contextual Info: GD54/74LS145 BCD-TO-DECIMAL DECODER/DRIVER Features Pin Configuration • Full Decoding of Input Logic • 80-m A Sink-Current Capability • All Outputs Are Off for Invalid BCD Input Con­ ditions • Low Power Dissipation of ’L S 1 4 5 .3 5 mW Typical

74LS147

Abstract: 74ls147 pin diagram FUNCTIONAL APPLICATION OF 74LS148 74ls148 74LS147 equivalent motorola 74ls147 74ls748 SN54/74LS147 FAST AND LS TTL ls74
Contextual Info: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are

TOP 242 PN

Abstract: TTL 74145 LS 74145 74LS145 SN74LSXXXD SN74LSXXXN SN54LSXXXJ 751B-03
Contextual Info: SN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR The SN54 / 74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is

SN7414

Abstract: sn7414 circuit SN414
Contextual Info: SN5414, SN54LS14, SN7414, 74LS14 HEX SCHMITT-TRIGGER INVERTERS D ECEM BER 1 9 8 3 -R E V IS E D MARCH 1988 Operation from Very Slow Edges SN&414, SN 54LS14 J OR W PACKAGE S N 7414 . . . N PACKAGE SN 74LS14 . D OR N PACKAGE • Improved Line-Receiving Characteris­

Contextual Info: • 8 -Nne-to-3-line Octal Priority Encoders IBLOCK DIAGRAM The H D 74LS148 encodes eight data lines to three-line 4-2-1 binary (octal). Cascading circuitry (enable input El and enable output EO) has been provided to allow octal expansion w ith ­ out the need for external circuitry. The data inputs and out­

pin diagram of ic 74ls148

Contextual Info: GD54/74LS148 8-TO-3 LINE PRIORITY ENCODER Features Pin Configuration • Priority Decoding of the Data Inputs • • • Code conversions Decimal-to-BCD Converter Group Serial Output active when any input is low VCc OUTPUT ENABLE EÖ GS 55 d3 d2 D, D5 Do

biffi

Contextual Info: DËj| tiTBSñSE OODVCmt, 7 | ~ 6 93 2 8 52 P ANASONI C INDL» ELECTRONIC LS TTL D N 74L S 5>U —X _ _ PANASONIC INDL/ELEK -CIO 72 ' 72C 0 7 0 4 6 P.T-66-21-57 dn 74LS148/ dn 74LS148S D N 7 4 L S 14 8 /D N 7 4 L S 1 4 8 S 8 -lin e to 3-lin e Octal P r io r ity Encoders

74LS14 not gate

Abstract: 74LS14 ttl 74ls14 74ls13 74ls14 ttl equivalent for 74LS13 TTL Schmitt-Trigger Inverters TTL Schmitt-Trigger LOW POWER SCHOTTKY 74 LS 14 Logic Gates 74LS14 datasheet
Contextual Info: SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

74LS00 7400 74S00

Abstract: 74LS04 74LS04 NOT gate 74LS00 74LSoo 74H04 74H00 TTL 74ls00 TTL 7404 TTL 74ls04
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,

IC 7404 7406

Abstract: 74LS00 7400 74S00 IC TTL 74LS00 ic 7404 74LS04 Hex Inverter Gates ic 74132 TTL 74h04 Fairchild 9002 ic 7404 fairchild 74LS132
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,

Contextual Info: LS TTL DN74LS Series 74LS145 74LS145 BCD to Decimal Decoders / D rivers • Description P -2 D N 74LS145 is a BCD to decim al decoder/ driver w ith open collector o u tp u ts. ■ • • • • Features ' W i Large o u tp u t cu rrent I q l iS 80m A m axim um

Contextual Info: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which perforins th logic INVERT function. Each in­ put has hysteresis which increases the noise im­ munity and tr&nsfotms a slowly changing Input signal

74ls145

Contextual Info: GD54/74LS145 BCD-TO-DECIMAL DECODER/DRIVER Features Pin Configuration • Full Decoding of Input Logic • 80-mA Sink-Current Capability • All Outputs Are Off for Invalid BCD Input Con­ ditions • Low Power Dissipation of ’LS145.35 mW Typical INPUTS

TTL 7404

Abstract: 7404 TTL TTL 7401 nand ttl 7400 TTL 741 TTL 7414 74IS244 CI 74LS04 TTL 7400 CI 74LS00
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,

1S2074

Abstract: 74LSOO HD74LS148
Contextual Info: • 8 -line-to-3-line Octal Priority Encoders IBLOCK DIAGRAM The H D 74LS148 encodes eight data lines to three-line 4-2-1 binary (octal). Cascading circuitry (enable input El and enable output EO) has been provided to allow octal expansion w ith ­ out the need for external circuitry. The data inputs and out­

74LS147

Abstract: 74ls147 pin diagram 74ls748 SN54/74LS147,SN54/74LS148 74LS148 motorola 74ls147 PIN 74LS147 74ls147 datasheet 74LS147 equivalent LS148
Contextual Info: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are

74LS145

Abstract: SN54LSXXXJ SN74LSXXXD SN74LSXXXN TTL LS 74145 74 LS 04 Logic Gates 74LS145DC 74 LS 14 Logic Gates TTL 74145 driver open-collector high voltage
Contextual Info: 8 < MOTOROLA, > SN54/74LS145 1-OF-IO DECODER/DRIVER OPEN-COLLECTOR The S N 54/74LS145, 1-o f-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is

7404 TTL CMOS

Abstract: TTL 7400 fairchild TTL 74h04 7404 ttl inverter TTL 7404 fairchild 9016 CI 74LS00 TTL 7404 fairchild 74H00 TTL TTL 9016 fairchild TTL 7401
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,

TTL 7410

Abstract: TTL 7401 TTL 7420 IC TTL 74LS00 TTL 7404 fairchild 9016 74LS00 TTL TTL 74LS04 TTL 7400 fairchild 7400 ecl inverter TTL 74h04
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,

74LS148

Abstract: encoder 74LS148 AM25LS148
Contextual Info: Am25LS148 • Am54LS/74LS148 Eight-Line To Three-Line Priority Encoder F U N C T IO N A L D E S C R IP T IO N D IS T IN C T IV E C H A R A C T E R IS T IC S • • Encodes e ig h t in p u ts in p r io r ity Provides a 3 -b it b in a ry ve cto r • • In dicates data present fo r all inputs

Contextual Info: SN54145, SN54LS145, SN7414S. 74LS145 BCD TO DECIMAL DECODERSfDRIVERS MARCH 1974 - REVISED MARCH 1988 F O R U SE A S LAM P, R E L A Y , OR MOS D R IV E R S Full Decoding of Input Logic SN54145, SN74145, and SN 74LS145 Have 80-mA Sink-Current Capability S N 54145, SN 54LS145 . . J OR W PACKAGE