74LS139 APPLICATION Search Results

74LS139

Abstract: demultiplexer truth table LS 74LS139 Truth table of 1 to 16 demultiplexer LS139 74ls139 datasheet SN54/74LS139 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS139 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder /Demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each

demultiplexer truth table

Abstract: 74ls139 datasheet 74ls139 decoder SN54/74LS139 transistor motorola 236 LS139 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS139 application
Contextual Info: SN54/74LS139 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder /Demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each

pin diagram of ic 74ls139

Abstract: decoder 3-8 74ls with nor gate 74ls139 motorola ttl application TTL IC 74
Contextual Info: MOTOROLA SN54/74LS139 DUAL 1-0F-4 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder/D e­ multiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each

Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The HD74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

74LS139 pin configuration with

Abstract: 74LS139 74ls139 decoder pin configuration 74ls139 decoder 54LS 74LS
Contextual Info: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Pin Configuration V çç SELECT DATA OUTPUTS ENABLE^_ _ _

Contextual Info: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Vçç SELECT DATA OUTPUTS ENABLE^_ _

Contextual Info: GD54/74LS139 DUAL 2-TO-4-UNE DECODERS/DEMULTIPLEXERS Feature • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Schottky Clamped for High Performance Pin Configuration SELECT V çç 25 2A 2B DATA OUTPUTS 2VQ 2V1 2Y2

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

LS139

Abstract: LS138 LS138-LS139 74LS139 DM74LS139N
Contextual Info: LS138-LS139 National Semiconductor 54 LS138/DM 54LS138/DM 74LS138, 54 LS139/DM 54LS139/DM 74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing appli­

Contextual Info: 139 139 CONNECTION DIAGRAM PINOUT A // 54S/74S139 d / 6 b c \/54LS/74LS139 6 i o ^ ' f ° 7 DUAL 1-0F-4 DECODER D E S C R IP TIO N — The ’139 is a high speed dual 1-of-4 decoder/dem ultiplexer. The device has tw o independent decoders, each accepting tw o inputs

74LS139

Abstract: M16A M16D MM74HC139 MM74HC139M MM74HC139MTC MM74HC139SJ MTC16 diode D254
Contextual Info: Revised February 1999 E M IC O N D U C T O R T M MM74HC139 Dual 2-To-4 Line Decoder General Description equivalent to the 74LS139. All inputs are protected from dam age due to static discharge by diodes to V qq and T he M M 74H C 139 d ecoder utilizes advanced silicon-gate

74HC139M

Abstract: 74hc139n
Contextual Info: A s e m I R C i c o n H d u S eptem ber 1983 I L D Revised February 1999 c t o r MM74HC139 Dual 2-To-4 Line Decoder equivalent to the 74LS139. All inputs are protected from dam age due to static discharge by diodes to V qq and General Description The M M 74H C 139 deco d e r utilizes advanced silicon-gate

74LS139

Abstract: of ic 74ls139 5101 fg
Contextual Info: <8> M O T O R O L A SN54/74LS139 D E S C R I P T I O N — The L S T T L / M S I S N 5 4 L S / 7 4 L S 1 3 9 is a high speed Dual 1-of*4 Decoder/Demultiplexer. T he device h as two independent decoders, each accepting tw o inputs and providing four mutually

Contextual Info: A I R EM I C O C H S eptem ber 1983 I L D N D U G Revised February 1999 T O R TM MM74HC139 Dual 2-To-4 Line Decoder equivalent to the 74LS139. All inputs are protected from dam age due to static discharge by diodes to V qq and General Description The M M 74H C 139 deco d e r utilizes advanced silicon-gate

75LS139

Abstract: pin diagram of ic 74ls139 74HC139 of ic 74ls139 GX414CD m74hc139n
Contextual Info: GENNUM C O R P O R A T I 16x1 VIDEO MULTIPLEXER EVALUATION BOARD O N by Ian Ridpath, Senior Applicahon Engineer, Video and Broadcast Products Group APPLICATION NOTE INTRODUCTION This application note de scribes the construction and use of If more than one device is used, the ADDRESS inputs for each

ic 74ls138

Abstract: 74LS138M 74LS139C N74LS139
Contextual Info: TYPES SN54LS138. SN54LS139. SM54S13I, SNS4S139, SN74LS138. SM74LS139, SN74SB8. SN74S139 DECODERS/DEMULTIPLEXERS TTL MSI _ B U L L E T IN NO. DL-S 7611804, D E C E M B E R 1 9 7 2 -R E V IS E O O C T O B E R 1976 • Designed Specifically for High-Speed:

C2051

Abstract: ASSEMBLY LANGUAGE FOR AT89C51 flash programmer circuit for AT89c51 74LS04 pin configuration variable power supply circuit at89 programmer 74LS04 NOT gate pin configuration 74LS04 data chips 74ls04 AT89C51/LV51
Contextual Info: Using a Personal Computer to Program the AT89C51/C52/LV51/LV52/C1051/C2051 Introduction This application note describes a personal computer-based programmer for the AT89C51/C52/LV51/LV52/C1051/C2051 Flash-based Microcontrollers. The programmer supports all flash memory

74LS139PC

Abstract: pin diagram of ic 74ls139 SN74LS139 IC-F10
Contextual Info: g MOTOROLA SN54LS139 SN74LS139 D E S C R I P T I O N — The L S T T L/M S I S N 5 4 L S /7 4 L S 1 39 is a high speed Dual 1-of-4 D ecoder/D em ultiplexer. T he device has two independent decoders, each accepting tw o inputs and providing four m utually

IC 74hct139

Abstract: 20 PIN LEADLESS CHIP CARRIER 74LS373 Decoder 8251A 1N916 74hct139
Contextual Info: HIGH SPEED CMOS DUAL 1-OF-4 DECODER Integrated Dev ice Technology. Inc IDT54/74HCT139 IDT72T339 i cr> CN CO FEATURES data-routing applications requiring very short propagation delay tim es, but needing very low power consum ption. The ID T 54/74H C T139 is pin and functionally com patible

54LS139

Abstract: 74HCT 74LS139 C1995 HCT139 MM54HCT139 MM74HCT139
Contextual Info: MM54HCT139 MM74HCT139 Dual 2-To-4 Line Decoder General Description The MM54HCT139 MM74HCT139 is a high speed silicongate CMOS decoder that is well suited to memory address decoding or data routing applications It possesses an input threshold and output drive similar to LS-TTL and the low

74LS139

Abstract: M16A M16D MM74HC139 MM74HC139M MM74HC139MTC MM74HC139N MM74HC139SJ MTC16 N16E
Contextual Info: Revised December 2003 MM74HC139 Dual 2-To-4 Line Decoder General Description Features The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually

74LS139

Abstract: M16A M16D MM74HC139 MM74HC139M MM74HC139MTC MM74HC139N MM74HC139SJ MTC16 N16E
Contextual Info: Revised February 1999 MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually

HC139

Abstract: MM54HC MM54HC139 MM74HC MM74HC139 54ls139
Contextual Info: MM74HC139 Dual 2-To-4 Line Decoder General Description This decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually associated with CMOS

Contextual Info: January 1988 MM54HC139/MM74HC139 Dual 2-To-4 Line Decoder General Description This decoder utilizes advanced silicon-gate CMOS technol­ ogy, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually associated with CMOS