74LS 11 Search Results

F74B

Contextual Info: SPEED/PACKAGE AVAILABILITY 54 f ;w 54H F,W 54LS F,W 54S F,W 74 74H 74LS 74S PIN CONFIGURATION A,F A,F A,F A,F 74.74H, 54/74LS, 54/748 A,F,W PACKAGE SWITCHING CHARACTERISTICS TEST CONDITIONS PARAMETER 54,54« W PACKAGE v C C - 5V, TA = 25°C 54/74 54/74H 54/74LS

Contextual Info: M MOTOROLA. SN54/74LS90 SN54/74LS92 SN54/74LS93 DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER The SN 54/74LS 90, S N 54/74LS 92 and S N 54/74LS 93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or

lm294oct

Abstract: d71054c D71055C lm294oct-12 74c928 7486 XOR GATE interfacing ADC 0808 with 8086 microprocessor 555 7490 7447 7 segment LED display Motorola 74LS76 NEC D71055C
Contextual Info: Integrated Circuits 74LS Series Featuring better performance than standard 7400 series devices, the 74LS series also uses about 1/5th the power. Part# Pins Description 74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS07 74LS08 74LS09 74LS10 74LS11 74LS12

LS623

Abstract: D2537 SN74LS620
Contextual Info: S N 54LS 620, SN 54LS621, SN 74LS 620, SN 74LS 621, SM 74LS623 OCTAL BUS TRANSCEIVERS D2537, AUGUST 1979-REVISEO MARCH 1988 SN 54LS620, S N 54LS621, S N & 4 L S 6 2 2 . . . J P AC K A G E S N 74LS 620, S N 74LS621, S N 7 4 L S 6 2 3 . . . D W O R N P AC K A G E

Contextual Info: AVG DDi Semiconductors Technical Data 192, 193 Synchronous Up/Down Decade and Binary Counters with CLEAR DV74LS192 DV74ALS192 DV74LS193 DV74ALS193 The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary

Contextual Info: AVG DDi Semiconductors Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are

54LS244

Contextual Info: LS244 National Semiconductor 54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description • Typical Iq i_ sink current 54LS 12 mA 74LS 24 mA ■ Typical Ioh (source current) 54LS - 1 2 mA 74LS - 1 5 mA ■ Typical propagation delay times

74ALS192

Abstract: IC 74LS192 LS192 ALS192 MODULO-16 DV74LS192 DV74LS192-93 LS193
Contextual Info: AVG Semiconductors DDT Technical Data The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The out­

4QFC

Abstract: S62D
Contextual Info: SN54LS595, SN54LS596, SN74LS595, SN74LS596 8 BIT SH IFT REGISTERS W ITH O U TPU T LATC H ES 02634, JANUARY 1981 - REVISED MARCH 1988 S N 54LS 595, SN64LS596 . . . J OR W PACKAGE SN 74LS 595, S N 74LS 596 . . . N PACKAGE 8-Bit Serial-ln, Parallel-Out Shift

Contextual Info: MOTOROLA SN54/74LS168 SN54/74LS169 BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN 54/74LS 168 and SN 54/74LS 169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U /D input to control the direction

74LS147

Abstract: 74LS148 74ls748 LS748 PIN 74LS147 LS148 ttl 74ls147 LS 74LS147 6200S ttl 74ls148
Contextual Info: <8 > MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the S N 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order

ls190

Abstract: 30132 10116
Contextual Info: 190,191 AVG Semiconductors DDT Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are

LS155

Abstract: 74ls155 74 ls 155 demultiplexer 74ls156
Contextual Info: MOTOROLA SN54/74LS155 SN54/74LS156 DUAL 1-0F-4 DECODER/ DEMULTIPLEXER The SN 54/74LS 155 and S N 54/74LS 156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an

20-PIN

Abstract: M74LS37P
Contextual Info: MITSUBISHI LSTTLs M 74LS 37P Q U A D RU PLE 2-IN P U T P O S IT IV E NAND B U FFER DESCRIPTION The M 74LS 37P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing four 2-in p u t positive N A N D and negative NOR buffer gates. FEATURES

74ls48 PIN OUT

Contextual Info: <8> M OTOROLA D E S C R IP T IO N — The S N 54LS /74LS 48 and S N 54LS /74LS 49 are BCD to 7-Segm ent Decoders consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. The LS49 offers active HIGH opencollector outputs for current-sourcing applications to drive logic circuits

SC74HC595

Abstract: SC74HC595C SC74HC595D sc74hc
Contextual Info: SC74HC595 8 3S SC74HC595 8 CMOS / 8 SOP-16-300-1.27 54LS/74LS SOP-16-225-1.27 54LS/74LS SSOP-16-300-0.65 SCK RCK SCK SI RCK SCLR DIP-16-300-2.54 TSSOP-16-225-0.65 G * 2~6V * 1µA * 15 * * SC74HC595 DIP-16-300-2.54 SC74HC595A SOP-16-225-1.27 fmax=55MHz VCC=5V

Contextual Info: g MOTOROLA SN54/74LS290 SN54/74LS293 DECADE COUNTER; 4-BIT BINARY COUNTER The S N 54/74LS 290 and S N 54/74LS 293 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two sec­ tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section

DL093D

Abstract: scans-048 74LS93N DSAGER00017 DL090D plh-1648
Contextual Info: m f f l k [ n > S e l e N t e n o r i i S » DL 090 D DL 093 D Internationale Vergleichstypen: SN 74LS 90 N SN 74LS 93 N S chaltkreise in Low -P ower-Schottky-Teehnologie DL 090 D Dezimalzähler DL 093 D 4 Bit-Binärzähler V orläufige technische Daten

SN74LS604

Contextual Info: SN54LS604, SN54LS606, SN54LS607, SN74LS604, SN74LS606, SN74LS607 OCTAL 2-INPUT MULTIPLEXED LATCHES D254-5, JULY 1979-REVISED MARCH 1988 T IM 9 9 6 0 4 , T IM 9 9 6 0 6 , T IM 9 9 6 0 7 SN 54LS 604, SN 54LS 606, SN 54LS607 . . JO PACKAGE SN 74LS 604, SN 74LS 606. SN 74LS607 . . . JD OR N PACKAGE

Contextual Info: M M O T O R O L A SN54/74LS168 SN54/74LS169 BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN 54/74LS 168 and SN 54/74LS 169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U /D input to control the direction

74ls795

Abstract: 74LS796 74ls797
Contextual Info: M MOTOROLA SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 TRI-STATE OCTAL BUFFERS The S N 54/74LS 795 thru S N 54/74LS 798 device types provide a second source for the 71 /8 1 LS95 thru 7 1 /8 1 LS98 series. These devices are octal low power Schottky versions of the 70/8095 thru 70/8098 3-STATE Hex

mitsubishi air conditioning

Abstract: 20-PIN M74LS51P Scans-000 74ls51p
Contextual Info: MITSUBISHI LSTTLs M 74LS 51P DUAL 2 -W ID E 2 -IN P U T /3 -IN P U T AND -O R -IN VER T GATE DESCRIPTION The M 74LS 51P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing dual 2-wide 2-in p u t/3 -in p u t A N D -O R -IN V E R T

SN74LS383

Contextual Info: TYPES SN54LS363. SN54LS364. SN74LS363, SN741S364 OCTAL D-TYPE TRANSPARUT IATCMESAND ED6E-TRI6CEBED FUP-FlOPS TTL MSI BULLETIN HO. OL-& 7*11*6«, OCTOBiR 107« • SNMLS363 . . . J PACKAGE SN74LS383 . . . J OR N PACKAGE TOP VIEW High VOH •• ■3.65 V Min ( 74LS')

SN74LS83

Abstract: SN54LS638 SN54LS639 SN74LS SN74LS638 SN74LS639 LS638
Contextual Info: SN54LS638, SN54LS639, SM74LS638. SN74LS639 OCTAL BUS TRANSCEIVERS D2636, JANUARY 1981 -REVISED MARCH 1988 Bidirectional Bus Transceivers in HighDensity 20-Pin Packages SN54LS638, SN 54LS639 . . . J PACKAGE S N 74LS638. SN 74LS 639 . . . DW OR N PACKAGE TOP VIEW