74L NAND Search Results

74 series TTL NOT gate

Abstract: DM74L00N SN7421N B145 DM74L01N DM74L02N DM74L03N DM74L04N one gate ttl 74l family
Contextual Info: National Semiconductor 74L Series T T L Low-Power The Series 74L family is designed for applications requiring very low power dissipation. Typically a system can be built with a factor-of-ten power saving over the conventional T T L integrated circuits,

cd4023bc

Abstract: 74LS CD4023B CD4025B
Contextual Info: February 1988 CD4023BM/CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM/CD4025BC Buffered Triple 3-Input NOR Gate Features 3.0V to 15V • Wide supply voltage range ■ High noise immunity 0.45 VDD typ. ■ Low power TTL fan out of 2 driving 74L compatibility

74als power consumption

Abstract: 74AS Characteristics Introduction about 74ls 74AS ALS TTL family characteristics 74LS ALS74 AN-476 C1995 DM54
Contextual Info: INTRODUCTION Since the introduction of the first bipolar Transistor-Transistor Logic TTL family (DM54 74) system designers have wanted more speed less power consumption or a combination of the two attributes These requirements have spawned other logic families such as the DM54 74L (low

74HC00

Abstract: 74HC00F 74HC00 toshiba
Contextual Info: TOSHIBA T C 74L V X 00F / F N / F S Quad 2 - Input Nand Gate The TC74LVX00 is a high speed CM O S 2-INPUT NAND GATE fabricated with silicon gate C 2MOS technology. Designed for use in 3.3 Volt systems, it achieves high speed operation while maintaining the CMOS low power dis­

DDR Schaltkreise

Abstract: DL014D DL132D 74LS132N Deutschen Demokratischen Republik DSAGER00016 74ls014 26713
Contextual Info: inn]D[klP3is ] ^ i0 ^ ^ 3 ls,Q n S ' DL 014 D DL 132 D Internationale Vergleichstypen; SN 74L S 014 N SN 74LS132 N Schaltkreise in Low -pow er-S chottky-Tschnologie DL 0 14 D 6 Schm itt-Trigger-Inverter Y = Ä DL 132 D 4 S chm itt-Trigger NAND-Gatter m it je 2 Eingängen

74h541

Abstract: 74LS series nand gates SN7423 4 input nor gate 7423 ic 7423 g 106IC
Contextual Info: SCRIES 54/74. 54H/74H, 54L/74L, 54LS/74LS, 54S/74S THAHSISTOR-TRAKSISTOH 106IC PARAM ETER MEASUREMENT INFORM ATION TEST TABLE V CC O PEN C O LLEC TO R INPUT CONDITIONS NAND In p u t un d e r test a t V i l m ax, ail o th e rs at 4 .5 V >OH O UTPUTS IN P U T

LS37

Abstract: LS40
Contextual Info: NOR, NAND Buffers PIN-O UT A N D L O G IC D IA G R A M S LS40 DUAL 4-INPUT NAND BUFFER V c c ZD 2C Die S iz e .045 x .052 NC 2B 2 A 2Y positive logic: Y = A B C D Recommended Operating Conditions ILS/54L • 3LS/74L 5 Unit Min S u p p ly voltag e, V c c N o rm a liz e d fa n -o u t fro m each o u tp u t N

PIN CONFIGURATION 7426

Abstract: 74ls TTL family 7426 74LS26 74ls gate symbols 74LS LS26 N7426N N74LS26D N74LS26N
Contextual Info: Signefics I 7426, LS26 Gates Quad T w o-Inp ut NAND G ate Open C olle cto r Product Specification Lo gic Products TY PE T Y P IC A L P R O P A G A T IO N D E LA Y T Y P IC A L SU P P LY C U R R E N T (T O T A L ) 7426 14ns 8m A 74LS26 16ns 1.6m A ORDERING CODE

1sbl

Abstract: LS132 schematic diagram inverter LS13 SN74LS19A SN74LS24A TS14 ls24a
Contextual Info: SN74LS1SA, SN74LS24A SCHMITT-TRIGGER POSITIVE NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS SDLS138 JANUARY 1981 - REVISED MARCH 1388 • Functionally and Mechanically Identical to 'L S 1 3, T S 1 4 , and L S 132, Respectively • Improved Line-Receiving Characteristics

AOI31

Abstract: RSC-15 74LS94 EK-044-9004 ic 74ls83 CSR b4c M240C 4520C M165C bf368
Contextual Info: n n EK-044-9004 CMOS Gate Array 5GV Series The RICOH gate array 5GV series complies with the CMOS 1.5/i rule, and offers high speed operation with a gate delay time of 1.0 ns. The 5GV series inherits the rich library of 5GF gate array series. The cell library is compatible with

SN54L01

Abstract: sn74l01 SN74L03
Contextual Info: CIRCUIT TYPES SN54L01, SN54L03, SN74L01, SN74L03 QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS SN 5 4 L0 1 , SN 74 L0 1 T FLAT PACKAGE T O P V IE W schematic (each gate) 4Y 4B 4A SN 5 4 L0 3 , S N 7 4 L 0 3 J O R N D U A L - IN - L IN E P A C K A G E

rs flip-flop IC 7400

Abstract: 74ls105 TTL LS 7400 74LS series logic gates 7400 fan-out 74LS 3 input AND gate IC TTL 7400 schematic 74LS04 fan-out 74ls series logic family 90 watts inverter by 12v dc with 6 transisters
Contextual Info: GENERAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS Ovar operating free-air temper­ ature range unless otherwise noted Supply Voltage Vq c (See Note 1) Input Voltage V|n (See Note 1) Interemitter Voltage (See Note 2) Resistor Node Voltage, 54121, 74121 (See Note 1)

74LV132

Abstract: 74LV132D 74LV132DB 74LV132N 74LV132PW aSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN
Contextual Info: Philips Semiconductors Preliminary Specification Quad 2-iriput NAND Schmitt-trigger QUICK REFERENCE DATA GND = 0 V; T .,* = 25°C; tr - t, < 2.5 ns FEATURES ! • • • • • • 15 CL = pF Vcc = 3.3 V propagation delay nA, nB to nY Wave and pulse shapers

cmos 74C00 NAND

Abstract: 74C00 cmos 74C00 74C02 complementary transistors used in temperature controlled fan truth table inverter gate 74 74l family cmos 74L series truth table nand gate CMOS 741
Contextual Info: CMOS INTEGRATED CIRCUITS QUAD TWO-INPUT NAND GATE QUAD TWO-INPUT NOR GATE HEX INVERTER PIN CONNECTION T O P VIEW Vcc 114 I3 12 P- GENERAL DESCRIPTION These logic gate s e rrp lo y c o m p l e m e n t a r y MOSi C MO S to achi eve w i d e po wer su p p ly op e ra ti n g range, low p o w e r c o n s u m p ti o n , high noise i m ­

cd4023bcn

Contextual Info: Revised April 2002 CD4023BC Buffered Triple 3-Input NAND Gate General Description Features These triple gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and Pchannel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered

pin diagram for all 74 series ttl gates

Abstract: SN74L04N SN7404N sn74h04n 14 pin SN74S04N TTL 74 series pin diagram of sn7404n DM7400N ttl nand gate with power dissipation 74 ttl inverter or gate
Contextual Info: National Semiconductor Integrated Circuits—74 Series D E S C R IP T IO N S e rie s 74 integrated circuits are designed and characterised for high-speed, general-pdrpose digital applications where high D C noise margin and relatively low power dissipation are important

Contextual Info: S G S-THOMSON M2E T> B 7^2^237 ÜD33S42 5 BISGTH S C S -T H O Ü S O N B«an i©ilLli©FO,^©0i0D©i T74LS26 QUAD 2-INPUT NAND BUFFER DESCRIPTION The T74LS26 is a high speed QUAD 2-INPUT NAND BUFFER with open collector output fabri­ cated in LOW POWER SCHOTTKY technology.

CD4011BCN

Abstract: 74LS series logic gates 3 input or gate CD4011BCM
Contextual Info: Revised March 2002 CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate General Description Features The CD4001BC and CD4011BC quad gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current

7438PC

Abstract: 74LS38PC 5438DM 74LS38 5438FM 54LS38DM 54LS38FM 7438DC 7438FC 74LS38DC
Contextual Info: 38 CONNECTIO N DIAGRAM P IN O U T A ¡4/7438 V^4/ 6 / / -b 2 ^ l/5 4 L S /7 4 L S 3 8 ous ?‘r/ QUAD 2-IN PU T NAND BUFFER With O pen-Collector Output ORDERING CODE: See S e ctio n 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE V cc = + 5.0 V ±5%, V cc = + 5.0 V ±10% ,

LVX165

Abstract: MC74LVX3245 lvx161284 lvx125 lvx245 LVX132 MC74LVX2 LVX541 74lv139 applications hex inverter
Contextual Info: HC Portfolio Comparison PART # LVX00 LVX02 LVX04 LVXU04 LVX05 LVX06 LVX07 LVX08 LVX10 LVX11 LVX14 LVX20 LVX21 LVX27 LVX32 LVX50 LVX74 LVX86 LVX107 LVX109 LVX112 LVX123 LVX125 LVX126 LVX132 LVX138 LVX139 LVX153 LVX154 LVX157 LVX158 LVX161 LVX163 LVX164 LVX165

SN7483N

Abstract: B143 SN7482N DM74S00N DM74S03N DM74S04N DM74S05N DM74S10N DM74S11N 2-bit binary full adder
Contextual Info: Semiconductors N ational Semiconductor Integrated Circuits - Digital T T L 74S Series T T L Ultra-High-Speed Series'74S Schottky TTL circuits are designed to achieve ultra-high speeds previously obtainable only with emitter coupled logic, yet they retain the

74F38

Contextual Info: P h ilip * S e m ic o n d u c to rs -S ig n e tlc s FAST P ro d u ct* P rod uct s p e c ific a tio n Quad 2-input NAND buffer open collector FEATURE • Industrial temperature range available (—40°C to +85°C) TYPE 74F38 TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT! TOTAL)

MA161

Abstract: DN74LS13
Contextual Info: LS TTL DN74LS Series DN74LS13 DN74LS13 &MHIS13 Dual 4 -input P o sitiv e NAND S ch m itt-T riggers H Description P-1 DN 74LS13 contains tw o 4-input positive isolation NAND circuits w ith Schm itt triggers. • Features • • • • • Ideal for w aveform shaping

IC CD4011B

Abstract: CD4011b
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD CD4011B CMOS IC QUAD 2-INPUT NAND BUFFERED B SERIES GATE „ DESCRIPTION The UTC CD4011B contains four independent 2-input NAND gates which perform the function Y=A • B in positive logic. „ SOP-14 FEATURES * 5V-10V-15V Parametric Ratings