74HC00 B1 Search Results

Contextual Info: 74HC00 Quad 2−Input NAND Gate High−Performance Silicon−Gate CMOS The 74HC00 is identical in pinout to the LS00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. http://onsemi.com

74HC00 NOT GATE

Abstract: 74HC00 74HCT00 TTL 74HC00 74HC00 national semiconductor 74HC00 B1 74HCT00N 74HC00DB 74HC00N 74HCT00D
Contextual Info: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 5 — 25 November 2010 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74HC00

Abstract: 74hc00 datasheet 74HC00N 74HCT00 tPHL 74hc00 74hct00n 74HCT00D 74hc00 gate TTL 74HC00 74HC00DB
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74HC00; 74HCT00 Quad 2-input NAND gate Product specification Supersedes data of 1997 Aug 26 2003 Jun 30 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A

TTL 74HC00

Abstract: 74HC00 74HC00N 74HCT00 74HC00 B1 74HC00 quad CMOS nand gate CI 74HC00 74HCT00D 74HCT00N 74HC00D
Contextual Info: Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL . They are specified in compliance with

74hc00 equivalent

Abstract: 74hc00 and gates 74HC00 74hc00 soic
Contextual Info: C T g B M H MOTOROLA SC -CLOGIO ÜS b3b72£E DGflPOtti E | T-HÌ-ZI MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC00 Quad 2 -In p u t NAINID Gate High-Perform ance Silicon-Gate C M O S J SUFFIX CERAMIC CASE 632-08 The MC54/74HC00 is identical in pinout to the LSOO. The device inputs are com•patible with standard CMOS outputs; with pullup resistors, they are compatible with

74HC00

Abstract: 74HCT00 74LV00 74LV00BQ 74LV00D 74LV00DB 74LV00N 74LV00PW JESD22-A114E 74LV001
Contextual Info: 74LV00 Quad 2-input NAND gate Rev. 03 — 20 December 2007 Product data sheet 1. General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00. The 74LV00 provides a quad 2-input NAND function.

6206a

Abstract: 56002 evm XC68HC705K1CDW jack p4 2.1mm MAX232CSE XC68HC705k XC68HC705 MC74HC00AD MBRS120T3 74HC00
Contextual Info: 56002 MEMORY WR~ RD~ WR~ RD~ X/Y~ X/Y~ DDB[0.23] DDB[0.23] DDB[0.23] DAB[0.15] DAB[0.15] DAB[0.15] WR~ RD~ Freescale Semiconductor, Inc. X/Y~ NOTE: MEMORY.SCH SSI_TX SSI_RX SSI_FS D/C SCK C_RST CKOUT SSI_TX SSI_RX SSI_FS D/C SCK C_RST CKOUT ANALOG

6206a

Abstract: 6206a 4 pin 56002 evm MAX232CSE AT29C256PC jack p4 2.1mm tx-2 MC74HC00AD XC68HC705k 74HC00
Contextual Info: 56002 MEMORY WR~ RD~ WR~ RD~ X/Y~ X/Y~ DDB[0.23] DDB[0.23] DDB[0.23] DAB[0.15] DAB[0.15] DAB[0.15] WR~ RD~ X/Y~ MEMORY.SCH SSI_TX SSI_RX SSI_FS D/C SCK C_RST CKOUT SSI_TX SSI_RX SSI_FS D/C SCK C_RST CKOUT ANALOG SSI_TX SSI_RX SSI_FS D/C SCK C_RST CKOUT

6206a

Abstract: IC 74HC00 max232cse 56002 evm XC68HC705K1CDW MAX232CSE T 6206a 4 pin 74HC00 tx-2 DSP56002 EVM
Contextual Info: LINE_IN J9 1 0.33uF C183 GNDA 3 RING 5 4 2 TIP 1 CMOUT 0.33uF C109 2 2 47.5K 47.5K 2 47.5K R112 R111 1 1 R113 GNDA 1.0uF C182 3 2 5 6 7 MC33078 U14B 22.1K 47pF NPO R123 1 2 C108 MC33078 U14A 1 0.33uF C206 0.33uF 47pF NPO R114 1 2 22.1K C205 2 1 1 150 2 150

resistors 10k

Abstract: 74HC00 H5 RESISTORS 74HC157AD 56K2EVM hack x-tal DAB14
Contextual Info: D5 R15 J17 3 2 1 GREEN LED IRQA~ IRQB~ NMI 2 2 1 2 2 4 6 8 10 12 14 16 1 3 5 7 9 2 4 6 8 10 Port-B 1 3 5 7 9 11 13 15 74HC157AD B0 SELECT A0 B1 Y2 B2 Y1 Y0 A1 A2 B3 Y3 A3 O/E U16 DS~ PS~ BR~ BN~ HACK~ HEN~ HR/W~ H6 H4 H2 H0 12 9 7 4 1 2 CKOUT RESET~ BUS_CTRL

74HC00

Abstract: c03f MAX1240 MAX1240BCPA MAX1241 MAX1241BCPA MAX1241EVL11-DIP MAX872CPA MCM6306DJ15
Contextual Info: 19-1160; Rev 1; 8/97 MAX1241 Evaluation System/Evaluation Kit _Features ♦ Proven PC Board Layout ♦ Complete Evaluation System The MAX1241 evaluation system EV system is a complete, low-cost, single-channel data-acquisition system

VG-230

Abstract: 23C8001 74HC00 74HC125 74HC05 datasheet U9 74HC244
Contextual Info: 8 7 6 5 4 3 2 1 D D C C BLOCK DIAGRAM VG-230 SYSTEM MEMORY I/O CONNECTORS PCMCIA CONNECTORS BUFFERS/PWR SUPPLY A_CFG1 B_CFG1 C_CFG1 D_CFG1 E_CFG1 F_CFG1 B B A A VADEM Title VG-230 SAMPLE SCHEMATIC - CONFIG. 1 THESE SCHEMATICS ARE PROVIDED AS A DESIGN GUIDE ONLY.

036 84, rondorex w21

Abstract: constant time delay wcrh wcrh t11 wcrh T1 Pseudo SRAM HN27C101AG-10 Hitachi DSA00198 HM678127UHJ BCRH
Contextual Info: Hitachi Microcomputer H8S/2655 Interface Volume Application Note ADE-502-060 Rev. 1.0 9/5/98 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in

10K SIP Resistor

Abstract: VMAX3232 74HC573 20 PIN DIODE j1 MCM6306DJ15 PC 74HC139 8ROM MAX872CPA MAX1240BCPA MAX1241
Contextual Info: 19-1160; Rev 1; 8/97 概要 _ 特長 _ MAX1241評価キット EVキット は3V、12ビット MAX1241アナログディジタルコンバータの機能を 評価するための実装済み、試験済みPCボードです。

811171622a-100fn

Abstract: schematic diagram tv monitor advance 15 2N3904 158 2n3904 a19 811171622 vga motorola 2N3904 158 transistor Motorola R64 motorola camera 74HC00
Contextual Info: Order this document as AN1903/D MOTOROLA SEMICONDUCTOR APPLICATION NOTE Coyote Entry Level Digital Camera Reference Design 1.0 Introduction Coyote is an entry-level digital camera reference design. The purpose of Coyote is to provide a convenient means to bring a camera system quickly

TMS320C x series

Abstract: 74HC00 74HC04 AD10 AN129 TMS320 X84256 INTERFACING MEMORY WITH 8051 THROUGH I2C PROTOCOL 74hc0042
Contextual Info: Application Note AN129 What is MPS E2? by Application Staff, November 1999 Introduction MPS E2 The X84256 Microprocessor Compatible Serial E2PROM is a 256K-bit nonvolatile serial memory organized as 32K x 8. However, due to the sequential nature of the device, the use of consecutive reads or

M74HC00

Contextual Info: SGS-THOMSON t^OO«LIOT ô iO(Si M54HC00 M74HC00 QUAD 2-INPUT NAND GATE . HIGH SPEED tpD = 6 ns (TYP.) AT Vcc = 5 V • LOW POWER DISSIPATION Icc = 1 nA (MAX.) AT Ta = 25 °C ■ HIGH NOISE IMMUNITY V nih = V nil = 28 % V cc (MIN.) ■ OUTPUTS DRIVE CAPABILITY

Contextual Info: M5 4 HC 132 M7 4 HC 132 S G S -T H O M S O N A 7 f RiflDMOîIlILiÊTIWRDDÊi QUAD 2-INPUT SCHMITT NAND GATE • HIGH SPEED tPD = 21 ns TYP. at VCC= 5V ■ LOW POWER DISSIPATION lcc = 1 pA (MAX.) at Ta = 25°C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

Contextual Info: M 54H C 00 M 74H C 00 S G S -T H O M S O N [^D K Q [i[L[E©¥[E@[iaD©i QUAD 2-INPUT NAND GATE • HIGH SPEED tpD = 8 ns (TYP.) at V c c = 5V ■ LOW POWER DISSIPATION Ice = 1 M (MAX.) at Ta = 25°C ■ HIGH NOISE IMMUNITY V n i H = VnIL= 280/o V CC (MIN.)

M74HC00

Contextual Info: Sb E G Z T> m 7^2^237 DG3T73D S'ìD • S G T H S C S -T H O M SO N HD»I[L[l RiO gi s G S-THÖHS0N M54HCÖÖ M74HC00 T -*i3 -Z ( QUAD 2-INPUT NAND GATE ■ HIGH SPEED tpD = 8 ns (TYP. at Vcc = 5V ■ LOW POWER DISSIPATION Ice = 1 i*A (MAX.) at Ta = 25°C

Contextual Info: SbE D • 7 ^ 2 3 7 □ □ a 'îû ? ! 1=14 ■ SGTH / T T S C S -T H O M S O N ^7# HO g ®i[Li(girMD(gi M54HC132 M74HC132 S G S-TH0nS0N T - ^ - Z / QUAD 2-INPUT SCHMITT NAND GATE ■ HIGH SPEED tPD = 21 ns (TYP. at VCc = 5V ■ LOW POWER DISSIPATION

TMS320C x series

Abstract: X84041 A26 W 74HC00 74HC04 AD10 AD11 AD12 AN57 TMS320
Contextual Info: Application Note AN57 2 What is MPS E ? by Gray Creager, May 1994 Introduction 2 The X84041 MPS E Microprocessor Compatible 2 Serial E PROM is a 4K-bit nonvolatile serial memory organized as 512 x 8. However, due to the sequential nature of the device, the use of

74HC132B

Contextual Info: M54HC132 M74HC132 SGS-THOMSON « im iO T O K S QUAD 2-INPUT SCHMITT NAND GATE • HIGH SPEED tpD = 11 ns TYP. AT V c c = 5 V ■ LOW POWER DISSIPATION Ice = 1fiA (MAX.) AT Ta = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTLLOADS ■ HIGH NOISE IMMUNITY V h (TYP.) = 0.9 V AT Vcc = 5 V

M74HC00

Abstract: M74HC00M1R M74HC00B1R 74LS00 74HC00 M54HC00 M54HC00F1R M74HC00C1R 74LS00 truth table M74HC00B1
Contextual Info: M54HC00 M74HC00 QUAD 2-INPUT NAND GATE . . . . . . . . HIGH SPEED tPD = 6 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUTS DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS