74HC 040 Search Results

74LV123

Abstract: 74LV123N 74LV123PW 7A-X
Contextual Info: Philips Semiconductors Product specification Dual retriggerable monostable multivibrator with reset 7AX FEATURES DESCRIPTION • O ptim ized for Low Voltage applications: 1 .Oto 5.5V The 74LV123 is a low-voltage Si-gate CM O S device and is pin and function com patible with the 74HC/HCT123.

mr 4040

Abstract: HCT4040 CTR12 4000B 74HC 74HC-HCT4040
Contextual Info: 74H C /H CT4040 MSI 12-STAGE B IN A R Y RIPPLE COUNTER FE A T U R E S • • TYPICAL O utput capability: standard 'CC category: MSI G E N E R A L D ES C R IPTIO N The 74HC/HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the ” 4 040" o f the

EP910PC-40

Abstract: EP910LI PACKAGE EP910 texas
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187, OCTOBER 1988-REVISED AUGUST 19S9 • High-Density (Over 900 Gates) Replacement for TTL and 74HC D U A L-IN -LIN E PAC KAG E (TO P V IE W I C 1 iC 2 ]V c c 39 H i 38 □ i

PM555

Abstract: cd74hct4046 4046A 74HCT4046A
Contextual Info: Technical Data F ile N u m b e r CD54/74HC 4046A CD54/74HCT 4046A 1854 Advance Inform ation/ Preliminary Data High-Speed CMOS Logic Phase-Locked-Loop with VCO C O M P N- m O p e ra tin g p o w e r s u p p ly vo lta g e ra ng e : Features: • O p e ra tin g fre q u e n c y ra n g e o f u p to

BPW22A

Abstract: cm .02m z5u 1kv pin configuration of BFW10 la4347 B2X84 TDA3653 equivalent TRIAC TAG 9322 HEF40106BP equivalent fx4054 core dsq8
Contextual Info: Contents Page Page New product index Combined index and status codes viii x Mullard approved components BS9000, CECC, and D3007 lists CV list Integrated circuits Section index xliii 1 5 Standard functions LOGIC FAMILIES CMOS HE4000B family specifications CMOS HE4000B family survey

Contextual Info: 5 bE 7 T 2 ‘ì S 3 7 ]} GDMDEÔS Ô7b « S 6 T H V -5 2 - 3 0 - 0 7 M54/74HCT646 M54/74HCT648 SGS-THOMSON HCT646 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HCT648 OCTAL BUS TRANSCEIVER/REGISTER (INVERTING-3 STATE) S Û S-THOMSON • LOW POWER DISSIPATION |c c = 4/iA (MAX.) at TA = 250C

Contextual Info: SbE D • rzj •JM. 7^237 GOMGQb? ■SGTH SCS-TH OM SON 6* i[LiCT[iMS0 S S 6 S-THOMSON M54HC242/243 M74HC242/243 T- S z -a -o s QUAD BUS TRANSCEIVER 3-STATE PRELIMINARY DATA ■ HIGH SPEED tpD = 10 ns (TYP.) at Vcc = 5V ■ LOW POWER DISSIPATION lCc = 4 /iA (MAX.) at TA = 25°C

Contextual Info: E 1 • 7 ^ 2 3 7 G040D2b 47b ■ SGTH s G s-THOMSON SGS-THOMSON M 54H C 194 M 74H C 194 'T - H C - ö 'l'O S 4 BIT PIPO SHIFT REGISTER ■ HIGH SPEED tpo = 13 ns TYP. at V c c = 5V ■ LOW POWER DISSIPATION Ic e = 4 piA (MAX.) at TA = 2 5 °C ■ HIGH NOISE IM M UN ITY

HC574

Abstract: ic HC574
Contextual Info: 5 b E P • 7 ^5 *^5 3 7 0 0 M 0 1 7 7 a n » S fiT H r= Z S C S -T H O M S O N *7# IM«m[I gTOR!]0(gS T - * iC - Ö 7 - ( f M54/74HC374/534 M54/74HC564/574 OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT HC534/HC564 INVERTING - HC374/HC574 NON-INVERTING S G

74HC7046A

Contextual Info: New Data CD54/74HC7046A CD54/74HCT7046A pciouT Old PC2QUT •2CS-41204 FUNCTIONAL DIAGRAM File Number 1 9 2 0 Phase-Locked Loop with VCO And Lock Detector Type Feature«: • Center frequency of 18 MHz fyp. at Vcc = 5 V • Choice o f two phase comparators:

hd74 series

Contextual Info: GENERAL INFORMATION • Outline of H itachi High S peed CMOS Logic • P re c a u tio n s in S y stem Design • Reliability • P a c k a g e Inform ation 10 OUTLINE OF HITACHI HIGH-SPEED CMOS LOGIC •FEATURES OF HIGH-SPEED CMOS LOGIC Hitachi's HS-C M OS logics—the H D 7 4 H C series and the H C T

DSP101

Abstract: DSP202
Contextual Info: B U R R -B RO W N wmmM DSP101 DSP102 r - r r ^ DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS FEATURES DESCRIPTION • ZERO-CHIP INTERFACE TO STANDARD DSP ICs: AD, AT&T, MOTOROLA, Tl • SINGLE CHANNEL: DSP101 • DUAL CHANNEL: DSP102

FPGA Virtex 6 pin configuration

Abstract: spartan 3a eeprom programmer schematic spartan 2 spartan application note eeprom programmer schematic diagram AT17 AT17A AT17C65 Altera flex10k
Contextual Info: Programming Specification for Atmel’s AT17 and AT17A Series FPGA Configuration EEPROMs The FPGA Configurator drive the DATA line Low. The system must provide a small pull-up current 1kΩ equivalent for the DATA line. The FPGA Configur ator is a ser ial

POTENTIOMETER 47KA

Abstract: D1990 DSP101 dsp32c circuit diagram 74HC DSP101JP DSP101KP DSP102 DSP102JP DSP102KP
Contextual Info: Hiv 'V B U R R -B R O W N • b DSP101 DSP102 I b DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS DESCRIPTION FEATURES The DSP101 and DSP 102 are high performance sam­ pling analog-to-digital converters designed for sim ­ plicity o f use with m odem digital signal processing

Contextual Info: 52E D BURR-BROWN CORP • 17313bS DOlt.701 T ■ - r - s i- o H - ié B U R R -B R O W N ■ b DAC703L ! b LCC Monolithic 16-Bit DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • MONOLITHIC CONSTRUCTION • HIGH ACCURACY: Linearity Error +0.0015% of FSR max

RS flip flop IC

Abstract: internal structure of ic 4017 RS FLIP FLOP LAYOUT hc 7400 sentry 4017 equivalent toggle type flip flop ic
Contextual Info: MMMHS MA GATE ARRAY SERIES 3/J1 METAL LAYER ANATRA-HARRIS SEM ICO NDUCTO R MA 0250-MA 0400 MA 0800-MA 1200 JANUARY 1986 Features Description • HIGH SPEED CMOS : 2 NS/GATE TYPICAL PROPAGATION DELAY. • LOW CONSUMPTION : - STAND BY CURRENT 10 nA/GATE - OPERATING CURRENT

1 bit full adder with carry

Abstract: 1-Bit full adder 1d1200a RS flip flop cmos
Contextual Info: MATRA MbE D M H S ES SfiböMSb Q Q Q Q S Ô 7 b SMMHS 'T - r X - MAY 1988 PRELIMINARY DATA SHEET OPEN ASIC MA GATE ARRAY SERIES - 3 M/ l METAL LAYER MA 0250 - MA 0400 - M A 0800 - M A 1200 H ATURSS • HIGH SPEED CMOS: 2 NS/GATE TYPICAL PROPAGATION DELAY • LOW CONSUMPTION:

DSP101

Abstract: DSP202 74HC163
Contextual Info: Or, Call Customer Servite al 1-8M-548-6132 USA Orili} DSP101 DSP102 The DSP101 offers a single conversion channel, with 18 bits of serial data output, allowing the user to drive 16-bit, 24-bit, or 32-bit DSP ports. The DSP102 offers two complete conversion channels, with either two

RS FLIP FLOP LAYOUT

Abstract: RS flip flop cmos 7400 2-input nand gate Ci 4008 breadboard binary and decimal counter Matra-Harris Semiconductor MATRA MHS HMT MATRA MHS HMT* 28 pins Matra-Harris 1 bit full adder
Contextual Info: MA GATE ARRAY SERIES 3/J1 METAL LAYER lÌlll IwSS^RRIS SEMICONDUCTOR MA 0250-MA 0400 MA 0800-MA 1200 JANUARY 1986 Features Description • HIGH SPEED CM OS : 2 NS/GATE TYPICAL PROPAGATION DELAY. • LOW CONSUMPTION : - STAND BY CURRENT 10 nA/GATE - OPERATING CURRENT

74LV14N

Contextual Info: 74LV14 Hex inverting Schmitt-trigger Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 PHILIPS Philips Semiconductors Product specification Hex inverting Schmitt-trigger 74LV14 FEATURES APPLICATIONS

1098AS-4R7M

Abstract: lithium polymer charger 10w C1608X7R1H104K GRM21BR61A475K EVQ-Q2K03W SCHEMATIC adapter 12v
Contextual Info: 19-4278; Rev 0; 9/08 MAX8819A Evaluation Kit Features The MAX8819A evaluation kit EV kit is a fully assembled and tested PCB for evaluating the MAX8819A power-management IC (PMIC). The MAX8819A PMIC is ideal for use in MP3 players and other handheld applications. In addition to the three step-down converters

AX400

Abstract: AX-400 CERDIP24 hhct
Contextual Info: 19-2249; Rev 1; 7/95 J V \J ÏX \J V \ CMOS Parallel Leading Dual 12-B lt M ultiplying D /A Convertors The Maxim MX7537/MX7547contain two 12-blt currentoutput m ultiplying digital-to-analog converters DAC In a single package. Input level shifters, data registers

vexta

Abstract: 74HC123 timing MAX8901 MAX8901A MAX8901B C1608X7R1H104K vexta c5
Contextual Info: 19-0998; Rev 0; 9/07 MAX8901 Evaluation Kit Features The MAX8901 evaluation kit EV kit is a fully assembled and tested printed-circuit board (PCB) that includes two circuits demonstrating the MAX8901A and the MAX8901B white LED (WLED) step-up DCDC converters. Both circuits share a central WLED

3bs3

Contextual Info: / M R C H I I _ D •M ICO N DUCTO R r General Description Features The VHC/VHCT245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technol­ ogy. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power