74AUP1 Search Results

74AUP1G04

Abstract: 74AUP1GU04 74AUP1Z04 74AUP1Z04GF 74AUP1Z04GM 74AUP1Z04GW
Contextual Info: 74AUP1Z04 Low-power X-tal driver with enable and internal resistor Rev. 3 — 22 July 2010 Product data sheet 1. General description The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in

74AUP1T45

Abstract: 74AUP1T45GF 74AUP1T45GM 74AUP1T45GW
Contextual Info: 74AUP1T45 Low-power dual supply translating transceiver; 3-state Rev. 3 — 4 November 2010 Product data sheet 1. General description The 74AUP1T45 is a single bit transceiver featuring two data input-outputs A and B , a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B) which enable

74AUP1G885

Abstract: 74AUP1G885DC 74AUP1G885GT JESD78
Contextual Info: 74AUP1G885 Low-power dual function gate Rev. 6 — 21 October 2010 Product data sheet 1. General description The 74AUP1G885 provides two functions in one device. The output state of the outputs 1Y, 2Y is determined by the inputs (A, B and C). The output 1Y provides the Boolean

74AUP1G374GF

Contextual Info: 74AUP1G374 Low-power D-type flip-flop; positive-edge trigger; 3-state Rev. 5 — 14 July 2010 Product data sheet 1. General description The 74AUP1G374 provides the single D-type flip-flop with 3-state output. The flip-flop will store the state of data input D that meet the set-up and hold times requirements on the

74AUP1G74

Abstract: 74AUP1G74DC 74AUP1G74GD 74AUP1G74GT
Contextual Info: 74AUP1G74 Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 5 — 26 July 2010 Product data sheet 1. General description The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data D , clock (CP), set (SD) and reset (RD) inputs and

74AUP1T58GF

Abstract: 74AUP1T58GM 74AUP1T58GW
Contextual Info: 74AUP1T58 Low-power configurable gate with voltage-level translator Rev. 3 — 18 October 2010 Product data sheet 1. General description The 74AUP1T58 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic

74AUP1T98GF

Abstract: 74AUP1T98GM 74AUP1T98GW
Contextual Info: 74AUP1T98 Low-power configurable gate with voltage-level translator Rev. 2 — 19 October 2010 Product data sheet 1. General description The 74AUP1T98 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic

74AUP1G240

Abstract: 74AUP1G240GF 74AUP1G240GM 74AUP1G240GW
Contextual Info: 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 2 — 13 September 2010 Product data sheet 1. General description The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH level at pin OE

74AUP1G97

Abstract: 74AUP1G97GF 74AUP1G97GM 74AUP1G97GW
Contextual Info: 74AUP1G97 Low-power configurable multiple function gate Rev. 5 — 20 October 2010 Product data sheet 1. General description The 74AUP1G97 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,

74AUP1G126

Abstract: 74AUP1G126GF 74AUP1G126GM 74AUP1G126GW
Contextual Info: 74AUP1G126 Low-power buffer/line driver; 3-state Rev. 3 — 3 September 2010 Product data sheet 1. General description The 74AUP1G126 provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A LOW level at pin OE

74AUP1G158GF

Abstract: 74AUP1G158GM 74AUP1G158GW
Contextual Info: 74AUP1G158 Low-power 2-input multiplexer; inverting Rev. 3 — 13 July 2010 Product data sheet 1. General description The 74AUP1G158 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

74AUP1G98

Abstract: 74AUP1G98FHX 74AUP1G98L6X JESD22-A114
Contextual Info: 74AUP1G98 TinyLogic Low Power Universal Configurable Two-Input Logic Gate Features Description ƒ ƒ 0.8V to 3.6V VCC Supply Operation ƒ High Speed tPD - 3.0ns: Typical at 3.3V ƒ ƒ Power-Off High-Impedance Inputs and Outputs The 74AUP1G98 is a universal configurable 2-input

"MARKING CODE AW"

Abstract: nxp marking code SOT363
Contextual Info: 74AUP1G373 Low-power D-type transparent latch; 3-state Rev. 01 — 29 November 2006 Product data sheet 1. General description The 74AUP1G373 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Contextual Info: 74AUP1G373-Q100 Low-power D-type transparent latch; 3-state Rev. 1 — 10 March 2014 Product data sheet 1. General description The 74AUP1G373-Q100 provides the single D-type transparent latch with 3-state output. While the latch-enable LE input is high, the Q output follows the data (D) input. When

Contextual Info: 74AUP1T98-Q100 Low-power configurable gate with voltage-level translator Rev. 1 — 19 May 2014 Product data sheet 1. General description The 74AUP1T98-Q100 provides low-power, low-voltage configurable logic gate functions. Eight patterns of 3-bit input determine the output state. The user can choose the logic

Contextual Info: 74AUP1G97 TinyLogic Low Power Universal Configurable Two-Input Logic Gate Features Description ̇ ̇ 0.8V to 3.6V VCC Supply Operation ̇ High Speed tPD - 3.1ns: Typical at 3.3V ̇ ̇ Power-Off High-Impedance Inputs and Outputs The 74AUP1G97 is a universal configurable 2-input

74AUP1G32

Abstract: 74AUP1G32GM 74AUP1G32GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G32 Low-power 2-input OR gate Rev. 01 — 2 August 2005 Product data sheet 1. General description The 74AUP1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

Contextual Info: NXP AUP1Z04 Evaluation board Easy test and evaluation of the 74AUP1Z04 This easy-to-use eval board lets you optimize for different system loads and evaluate the part under different test conditions. Key features } Wide supply voltage range: 0.8 V to 3.6 V

74AUP1G125

Abstract: 74AUP1GU04 74AUP1Z125 74AUP1Z125GF 74AUP1Z125GM 74AUP1Z125GW JESD22-A114E
Contextual Info: 74AUP1Z125 Low-power X-tal driver with enable and internal resistor Rev. 02 — 7 August 2008 Product data sheet 1. General description The 74AUP1Z125 combines the functions of the 74AUP1GU04 and 74AUP1G125 with enable circuitry and an internal bias resistor to provide a device optimized for use in

74AUP1G0832

Abstract: 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW
Contextual Info: 74AUP1G0832 Low-power 3-input AND-OR gate Rev. 01 — 8 November 2006 Product data sheet 1. General description The 74AUP1G0832 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G38GF

Abstract: 74AUP1G38GM 74AUP1G38GW JESD22-A114E MO-203
Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 02 — 14 June 2007 Product data sheet 1. General description The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to

74AUP1G158GF

Abstract: 74AUP1G158GM 74AUP1G158GW
Contextual Info: 74AUP1G158 Low-power 2-input multiplexer; inverting Rev. 01 — 7 November 2006 Product data sheet 1. General description The 74AUP1G158 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP1G3208

Abstract: 74AUP1G3208GF 74AUP1G3208GM 74AUP1G3208GW
Contextual Info: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 01 — 29 November 2006 Product data sheet 1. General description The 74AUP1G3208 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

001aad993

Abstract: 74AUP1T98GF 74AUP1T98GM 74AUP1T98GW JESD22-A114E
Contextual Info: 74AUP1T98 Low-power configurable gate with voltage-level translator Rev. 01 — 6 March 2008 Product data sheet 1. General description The 74AUP1T98 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic