74AUP1 Search Results

74AUP1G80

Abstract: 74AUP1G80GF 74AUP1G80GM 74AUP1G80GW MO-203
Contextual Info: 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP1G19GM

Abstract: 74AUP1G19GW JESD22-A114E
Contextual Info: 74AUP1G19 Low-power 1-of-2 decoder/demultiplexer Rev. 01 — 13 August 2008 Product data sheet 1. General description The 74AUP1G19 provides a 1-of-2 decoder/demultiplexer with a common output enable. It buffers the data on input pin A and passes it either to output pin 1Y true or 2Y

74AUP1G126

Abstract: 74AUP1G32 JESD22-A114E 74AUP1T1326
Contextual Info: 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 — 20 January 2009 Product data sheet 1. General description The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry.

74AUP1G58

Abstract: 74AUP1G58GF 74AUP1G58GM JESD22-A114E
Contextual Info: 74AUP1G58 Low-power configurable multiple function gate Rev. 02 — 26 March 2009 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,

74AUP1G126

Abstract: 74AUP1G126GF 74AUP1G126GM 74AUP1G126GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G126 Low-power buffer/line driver; 3-state Rev. 02 — 28 June 2006 Product data sheet 1. General description The 74AUP1G126 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all

74AUP1G00GW

Abstract: 74AUP1G00 74AUP1G00GF 74AUP1G00GM
Contextual Info: 74AUP1G00 Low-power 2-input NAND gate Rev. 3 — 7 October 2010 Product data sheet 1. General description The 74AUP1G00 provides the single 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G34

Abstract: 74AUP1G34GF 74AUP1G34GM 74AUP1G34GW
Contextual Info: 74AUP1G34 Low-power buffer Rev. 4 — 14 July 2010 Product data sheet 1. General description The 74AUP1G34 provides a low-power, low-voltage single buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74AUP1T34GF

Abstract: 74AUP1T34GM MO-203
Contextual Info: 74AUP1T34 Low-power dual supply translating buffer Rev. 2 — 19 August 2010 Product data sheet 1. General description The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is designed to track VCC A . Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y)

JESD22-A114E

Contextual Info: 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 2 — 9 July 2010 Product data sheet 1. General description The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to

74AUP1G0832

Abstract: 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW
Contextual Info: 74AUP1G0832 Low-power 3-input AND-OR gate Rev. 3 — 5 October 2010 Product data sheet 1. General description The 74AUP1G0832 provides the Boolean function: Y = A x B + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND.

3-input orgate

Abstract: SOT-120 74AUP1G332 74AUP1G332GF 74AUP1G332GM 74AUP1G332GW
Contextual Info: 74AUP1G332 Low-power 3-input OR-gate Rev. 3 — 7 October 2010 Product data sheet 1. General description The 74AUP1G332 provides a single 3-input OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74AUP1G58L6X

Abstract: 74AUP1G58 74AUP1G58FHX JESD22-A114 xnor
Contextual Info: 74AUP1G58 TinyLogic Low Power Universal Configurable Two-Input Logic Gate Features Description ƒ ƒ 0.8V to 3.6V VCC Supply Operation ƒ High Speed tPD - 3.1ns: Typical at 3.3V ƒ ƒ Power-Off High-Impedance Inputs and Outputs The 74AUP1G58 is a universal configurable 2-input

Contextual Info: 74AUP1G126 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed (Top View) for low power and extended battery life in portable applications. The 74AUP1G126 is a single non-inverting buffer/bus driver designed

74AUP1G86SE

Contextual Info: 74AUP1G86 SINGLE 2 INPUT EXCLUSIVE-OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G86 is a single 2-input positive exclusive-OR gate with a

Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP1G58

Abstract: 74AUP1G58GF 74AUP1G58GM
Contextual Info: 74AUP1G58 Low-power configurable multiple function gate Rev. 4 — 11 October 2010 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,

74AUP1G14

Abstract: 74AUP1G14GF 74AUP1G14GM 74AUP1G14GW MO-203
Contextual Info: 74AUP1G14 Low-power Schmitt trigger inverter Rev. 4 — 13 July 2010 Product data sheet 1. General description The 74AUP1G14 provides a single inverting Schmitt trigger which accepts standard input signals. It is capable of transforming slowly changing input signals into sharply defined,

74AUP1G17

Abstract: 74AUP1G17GF 74AUP1G17GM 74AUP1G17GW MO-203
Contextual Info: 74AUP1G17 Low-power Schmitt trigger Rev. 4 — 15 July 2010 Product data sheet 1. General description The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

JESD22-C101E

Contextual Info: Demonstrate seven different logic functions NXP demo board for the configurable logic device 74AUP1T97 NXP demo board for the configurable logic device 74AUP1T97 Key features and benefits } Wide supply voltage range: 2.3 to 3.6 V } High noise immunity } Excellent ESD protection

74AUP1G57

Abstract: 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW JESD22-A114-C transistor VT 209 M CDM 12.6 Philips
Contextual Info: 74AUP1G57 Low-power configurable multiple function gate Rev. 01. — 16 January 2006 Preliminary data sheet 1. General description The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP1G332

Abstract: 74AUP1G332GF 74AUP1G332GM 74AUP1G332GW JESD22-A114-C
Contextual Info: 74AUP1G332 Low-power 3-input OR gate Rev. 01.00 — 27 February 2006 Preliminary data sheet 1. General description The 74AUP1G332 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

Contextual Info: 74AUP1G58 TinyLogic Low Power Universal Configurable Two-Input Logic Gate Features Description ̇ ̇ 0.8V to 3.6V VCC Supply Operation ̇ High Speed tPD - 3.1ns: Typical at 3.3V ̇ ̇ Power-Off High-Impedance Inputs and Outputs The 74AUP1G58 is a universal configurable 2-input

74AUP1G00

Abstract: 74AUP1G00GM 74AUP1G00GW JESD22-A114-C MO-203 SC88A
Contextual Info: 74AUP1G00 Low-power 2-input NAND gate Rev. 01 — 11 July 2005 Product data sheet 1. General description The 74AUP1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G158GF

Abstract: 74AUP1G158GM 74AUP1G158GW JESD22-A114E
Contextual Info: 74AUP1G158 Low-power 2-input multiplexer; inverting Rev. 02 — 2 July 2009 Product data sheet 1. General description The 74AUP1G158 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data