74ALS163 Search Results

LS1639

Abstract: 74ALS1639
Contextual Info: TYPES SN 54A LS1638, S N 54A LS1639, SN 74 A LS1 638 , S N 7 4 A LS 1 639 OCTAL BU S TRANSCEIVERS D2661, DECEMBER 1982-REVISED DECEMBER 1983 Bidirectional Bus Transceivers in High-Density 20-Pin Packages S N 54A LS 1638, S N 54A LS 1639 J PAC KA G E S N 74A LS 1638, S N 74ALS1639

ALS161

Abstract: MS-012-AB 74ALS 74ALS161 74ALS161B 74ALS161BD 74ALS161BN 74ALS163B 74ALS163BD 74ALS163BN
Contextual Info: Signetics bbSBTSM OGMÜSlb fi • SIC3 1ÖE D NAPC/ SIGNETICS 74ALS161 B,74ALS163B Counters ALS Products FEATURES • Synchronous counting and loading • Two count enable Inputs for n-blt cascading • Positive edge-triggered d ock • Asynchronous Reset 'ALS161B

74ALS1639

Abstract: 74245 rca 645 74245 HC 74LS639 74LS640 74LS641 74LS642 74LS643 74LS645
Contextual Info: - 274- 74639 Octal 0. G./3-State Elus Transceiver 1 4 4 '1? I I 8 Iö ! ft f t i ijjt in in in in in m o B—A l± 0 . C. T A -»B l± 3 -State 74ALS639-1 74ALS1639 1 I i 48mA ¡1 I o l 24mA Io l FU N C T IO N TABLE O P E R A T IO N CONTROL 6 3 ‘i 641 645

TEXTOOL zif socket

Abstract: 74ALS 74ALS161B 74ALS161BD 74ALS161BN 74ALS163B 74ALS163BD 74ALS163BN 4CT15 74als163
Contextual Info: 74ALS161 B,74ALS163B Counters Signetics ALS Products FEATURES 4-Bit Binary Counters • Synchronous counting and loading Product Specification • Two count enable inputs for n-bit cascading • Positive edge-triggered clock • A synchronous Reset 'ALS161B

Contextual Info: INTEGRATED CIRCUITS 74ALS161B/74ALS163B 4-bit binary counter Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B 74ALS161B/74ALS163B 4-bit binary counter, asynchronous reset

74ALS163BN

Abstract: 74ALS 74ALS161B 74ALS161BD 74ALS161BN 74ALS163B 74ALS163BD
Contextual Info: 74ALS161 B,74ALS163B Counters FEATURES • Synchronous counting and loading • Tw o count enable inputs or n-bit cascading • Positive edge-triggered clock • A synchronous Reset ('A LS161B • Synchronous Reset ('A LS163B ) • High speed synchronous expansion

Contextual Info: Philips Sem iconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B 74ALS161B/74ALS163B 4-bit binary counter, asynchronous reset 4-bit binary counter, synchronous reset FEATURES DESCRIPTION • Synchronous counting and loading Synchronous presettable 4-bit binary counters 74A LS161 B,

74ALS163B

Contextual Info: Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B 74ALS161B/74ALS163B 4-bit binary counter, asynchronous reset 4-bit binary counter, synchronous reset FEATURES DESCRIPTION • Synchronous counting and loading Synchronous presettable 4-bit binary counters 74ALS161B,

74ALS1639

Abstract: 74ALS1638
Contextual Info: TYPES SN54ALS1638. SN54ALS1639, 74ALS1638, 74ALS1639 OCTAL BUS TRANSCEIVERS D 2 6 6 1 , D E C E M B E R 1 9 8 2 -R E V IS E D D E C E M B E R 198 3 Bidirectional Bus Transceivers in High-Density 20-Pin Packages S N 5 4 A L S 1 638. S N 5 4 A L S 1 6 3 9

D26G1

Contextual Info: TYPES SN54ALS1G38, SN 54A LS 1639, SN 74A LS1638, SN74A LS1639 OCTAL BUS TRANSCEIVERS D 2 6 6 1 , D EC EM B ER 1 9 8 2 -R E N A S E D DEC EM B ER 1 9 8 3 Bidirectional Bus Transceivers in H ig h -D e n s ity 2 0 -P in Packages SN 54A LS1 6 3 8 , S N 54A LS 1639

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir­ c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open

ci la 7610

Contextual Info: c +e MITSUBISHI ALSTTLs . op,00° M 74A L S 620A -1P v ie N v t ^s ^ - 3 _ OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS6Í20A-1P is a semiconductor integrated cir­ cuit consisting of eight bus transm itter/receiver circuits

ci la 7610

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state

Contextual Info: MITSUBISHI íDGTL LOGICI TI DEI't.E4*1ñ27 D0ia3flD S MITSUBISHI ALSTTLs M 624 9 82 7 M IT S U B IS H I DG TL L O G IC 7 4 A 91D L S 1 1 3 A P 12380 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP -FLO P W IT H SET T -H (* -o 7 -o y DESCRIPTION PIN CONFIGURATION (TOP VIEW)

74ALS640

Contextual Info: MITSUBISHI -CDGTL LOGIC} dT | ba^flS? D O i a k b B 4 M ITSUBISHI A L ST T Ls sc* -s s 5 " : . M 7 4 A LS6 4 7 P ,o.9B OCTAL BUS TR A N SC EIV ER /R EG IST ER WITH OPEN COLLECTOR OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGTC) DESCRIPTION The M74ALS647P is a semiconductor integrated circuit

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A L S 1 0 0 2 À P a D eE| tk24=]aS7 0015712 > | MITSUBISHI IDGTL LOGIC} 11 QUADRUPLE 2-IN P U T PO SITIVE NOR BUFFER 7 ^ V 3 - /S DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS1002AP is a semiconductor integrated cir­ cuit consisting of four 2-input positive-logic NOR buffer

J 5027 R

Abstract: BEM 6K
Contextual Info: MIT SUBISH I íDGTL L O G I C } T I d ËT| ^5^027 ~JZ.SZt~3/ G0127SS □ MITSUBISHI ALSTTLs M 74A L S 1621A P I 62 49 8 2 7 M I T S U B I S H T T D G T L T o G r ^ ~ 910 12755 D OCTAL BUS TRANSCEIVER W ITH OPEN COLLECTOR OUTPUT NONINVERTED) DESCRIPTION

Contextual Info: MITSUBISHI -CDGTL L O G I O TI DE | bSMTfla? 001E4b4 □ M IT SU B ISH I ALSTTLs M74ALS241AP 6249827 MITSUBISHI DGTL LOGIC 91D 12464 D O CTAL B U F F E R /L IN E D R IV E R W IT H 3 -ST A T E O U T PU T (N O N IN V E R T E D ) DESCR IPTIO N The M74ALS241AP is a semiconductor integrated circuit

Contextual Info: MITSUBISHI ALSTTLs & M74ALS169BP T ' - v ’S '- J J - o SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER 6249827 MITSUBISHI DG TL LOGIC DESCRIPTION Th e M 74A L S 169 B P is a sem iconductor integrated circuit of a synchronous p resettable u p /d o w n

74als561

Contextual Info: MITSUBISHI íDGTL LOGIC} "DÌI bSMTñE? 00123ki7 5 TI W~ M IT S U B IS H I* !L. S T T L s M74ALS38AP 91D 12367 D 6249827 MITSUBISHI DGTL LOGIC QUADRUPLE 2 -IN P U T P O S ITIV E NAND BUFFER W IT H OPEN COLLECTOR OU TPUT T - - V 3 - / S DESCRIPTION PIN CONFIGURATION (TOP VIEW)

Contextual Info: "d ë J M ITS UBISHI -CDGTL L O G I O bEMTfla? ooiBS'in a S^Ls MITSUBISHI ALSTTLs M 74ALS133P r _ 6249827 MITSUBISHI - y j - / r SINGLE 13-IN PU T POSITIVE NAND GATE DGTL LOGIC DESCRIPTION Th e M 7 4A LS 133P is a sem iconductor integrated circuit

m74als

Abstract: M74ALS109AP 74ALS640
Contextual Info: M IT S U B IS H I {D G T l T o G IcT ^ I b H 1 SS? M 6249827 MITSUBISHI 7 4 A CDGTL LOGIC 91D J STTLs L S 1 0 9 A 12 37 4 P D DUAL J-R POSITIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET AND RESET T -V & -0 7 - Ô ? DESCRIPTION PIN CONFIGURATION TOP VIEW) The M74ALS109AP is a semiconductor Integrated circuit

gt 568

Abstract: m74als568ap m74als568a
Contextual Info: MITSUBISHI -CDGTL L O G I O de! TI tsMiaa? QGiasai 4 |~~ M IT S U B IS H I ALSTTLs ~ J- M 74A LS 568A P S Y N C H R O N O U S P R E S E T T A B L E U P /O O W N D EC A D E C O U N TE R _ W IT H 3 -S T A T E O U T P U T 1H249827 MITSIJBISHI

M74ALS1032AP

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1 0 3 2 AP M I T S U B I S H I - C D G T L L O G I C } T I D È I ” L ^ M ^ ñ S ? 1 2 7 5 fi QUADRUPLE 2-IN P U T POSITIVE OR BUFFER _ DESCRIPTION _ _ _ _ PIN CONFIGURATION TOP VIEW The M74ALS1032AP is a semiconductor integrated cir­