74ALS11 Search Results

k0215

Abstract: 74ALS112A 74ALS 74ALS112AD 74ALS112AN
Contextual Info: INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook Philips Semiconductors 1996 June 27 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop DESCRIPTION 74ALS112A

SOT27-1 DIP14

Abstract: 74ALS 74ALS11A 74ALS11AD 74ALS11AN SC00023
Contextual Info: INTEGRATED CIRCUITS 74ALS11A Triple 3-Input AND gate Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Triple 3-input AND gate TYPE 74ALS11A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT

Contextual Info: Philips Semiconductors Product specification Triple 3-input AND gate TYPE 74ALS11A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 5.5ns 1.3mA 74ALS11A PIN CONFIGURATION ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCc = 5V ±10%,

Contextual Info: Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop DESCRIPTION 74ALS112A PIN CONFIGURATION The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock UFn , set (5D), and reset (RD) inputs, true (Qn) and complementary (Gn) outputs.

MS-012-AB

Abstract: 74ALS 74ALS11 74ALS11A 74ALS11AN SOL-24
Contextual Info: 74ALS11A Signetics Triple 3-Input AND Gates Product Specification ALS Products FUNCTION TABLE O U TPU T INPUTS TYPICAL PROPAGATION DELAY TYPE A B c Y H H H H L X X L X L X L X X L L NOTES: H = High voltage level L = Low voltage level X = Don't care TYPICAL SUPPLY CURRENT

74ALS11

Contextual Info: Philips Sem iconductors Product specification Triple 3-input AND gate TYPE 74ALS11A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 5.5ns 1.3mA PIN CONFIGURATION 1A [T 74ALS11A O RDER CODE CO M M E R C IA L RANGE V cc = 5V ±10%, Tamb = ° ° c to +70°C

74ALS

Abstract: 74ALS112A N74ALS112AD N74ALS112AN
Contextual Info: 74ALS112A Flip-Flop Dual J-K Negative Edge-triggered Flip-Flop Preliminary Specification DESCRIPTION TYPE TYPICAL s u p p l y c u r r e n t TOTAL TYPICALfMAX The 74ALS112A, Dual Negative Edge50MHz 74ALS112A Triggered JK-Type Flip-Ftop.Jeatures indi­ vidual J, K, Clock (CPn), Set (SD) and Reset U H U C n in u i n r u n n i n i i w . .

74ALS

Abstract: 74ALS11A 74ALS11AD
Contextual Info: 74ALS11A Triple 3-Input AND Gates Product Specification F U N C T IO N T A B L E A TYPE INPUTS B C Y H OUTPUT H H H L X X L X L X L X X L L N O TES: H = High voltage level L = Low voltage level X = Don't care T Y P IC A L P R O P A G A T IO N DELAY 74ALS11A

Contextual Info: M IT SU BI S HI O G TL LOGIC} TI ]>e | b E4 c1äS7 0D12377 S jp MITSUBISHI ALSTTLs M 6249827 MITSUBISHI I 7 4 A L S 1 1 2 A P <DGTL LOGIC 91D 12377 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP-FLO P W IT H SET AND RESET - - DESCRIPTION The M 74ALS112AP is a semiconductor integrated circuit

SN54ALS114A

Abstract: SN74ALS114A
Contextual Info: Owe XLSN54ALS114A, SN 74ALS114A DUAL J K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET, COM MON CLEAR, AND COM MON CLOCK D 2 6 6 1 , D EC EM BE R 1 9 8 2 -R E V IS E D M A Y 1 9 8 6 • Fully B u ffe re d to O ffe r M a x im u m Isolation fro m External D isturbance

Contextual Info: 74ALS112A, SN54ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FUP-FLOPS WITH CLEAR AND PRESET 02661, A PRIL 1982 - REVISED MAY 1986 • Fully Buffered to Offer Maximum Isolation from External Disturbance • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers,

Contextual Info: TC74VHC11F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC11F,TC74VHC11FN,TC74VHC11FT Triple 3-Input AND Gate The TC74VHC11 is an advanced high speed CMOS 3-INPUT AND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

74ALS11

Abstract: TC74VHC11F TC74VHC11FT
Contextual Info: TC74VHC11F/FT 東芝CMOSデジタル集積回路 シリコン モノリシック TC74VHC11F,TC74VHC11FT Triple 3-Input AND Gate TC74VHC11 はシリコンゲート CMOS 技術を用いた超高速 CMOS 3 入力 AND ゲートです。CMOS の特長である低い消費電力

74ALS11

Abstract: TC74VHC11F TC74VHC11FN TC74VHC11FS TC74VHC11FT
Contextual Info: TOSHIBA TC74VHC11F/FN/FS/FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHC11F, TC74VHC11FN, TC74VHC11FS, TC74VHC11FT TRIPLE 3 -INPUT AND GATE The TC74VHC11 is an advanced high speed CMOS 3-INPUT AND GATE fabricated with silicon gate C2MOS technology.

SN54ALS112A

Abstract: SN74 SN74ALS112A
Contextual Info: SN54ALS112A, 74ALS112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2 6 6 1 , A P R IL 1 9 8 2 — R E V IS E D M A Y 1 9 8 6 • Fully Buffered to Offer Maxim um Isolation from External Disturbance • Package Options Include Plastic "Sm all

SN54ALS11A

Abstract: SN54AS11 SN74ALS11A SN74AS11
Contextual Info: is 1 SNS4ALS11A, SN54AS11, 74ALS11A, SN74AS11 TRIPLE 3 INPUT POSITIVE AND GATES M A R C H 1 9 8 4 — R E V IS E D M A Y 1 9 8 6 P a c k a g e O p tio n s In c lu d e P la s tic " S m a ll O u tlin e " P a c k a g e s , C e ra m ic C h ip C a rrie rs , a n d S ta n d a rd P la s tic a n d C e ra m ic 3 0 0 -m il

74ALS11

Abstract: TC74VHC11F TC74VHC11FN TC74VHC11FT
Contextual Info: TOSHIBA T C 74V H C 11F/FN/FT TO SHIBA CM OS D IG ITAL INTEGRATED CIRCUIT T C 7 4 V H C 1 1 F , TRIPLE 3 -INPUT AND T C 7 4 V H C 1 1 F N , SILICON M ONOLITHIC T C 7 4 V H C 1 1 F T Note The JEDEC SOP (FN) is not available in Japan. GATE The TC74VHC11 is an advanced high speed CMOS 3-INPUT

STK411-230E

Abstract: STK411-220E stk442-130 PAL005A UPC2581V FN1016 STRG6153 RSN313H25 STK407-070B MCZ3001D
Contextual Info: R Serving The Electronic Industry Since 1982 Ordering at Dalbani is so easy Go to : www.dalbani.com Search & check stock Busque y revise nuestro inventario A Search Enter your Item number and click GO Entre el numero del producto y haga clicsobre GO The system will take you straight to the Item that you are looking for

Contextual Info: TC74VHC11F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC11F,TC74VHC11FN,TC74VHC11FT Triple 3-Input AND Gate The TC74VHC11 is an advanced high speed CMOS 3-INPUT AND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir­ c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open

ci la 7610

Contextual Info: c +e MITSUBISHI ALSTTLs . op,00° M 74A L S 620A -1P v ie N v t ^s ^ - 3 _ OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS6Í20A-1P is a semiconductor integrated cir­ cuit consisting of eight bus transm itter/receiver circuits

ci la 7610

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state

Contextual Info: MITSUBISHI íDGTL LOGICI TI DEI't.E4*1ñ27 D0ia3flD S MITSUBISHI ALSTTLs M 624 9 82 7 M IT S U B IS H I DG TL L O G IC 7 4 A 91D L S 1 1 3 A P 12380 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP -FLO P W IT H SET T -H (* -o 7 -o y DESCRIPTION PIN CONFIGURATION (TOP VIEW)

m74als191p

Contextual Info: ÍDGTL LOGIC} 91D TI De | 12446 b241fl27 □ 0 1 2 4 4b ñ r D MITSUBISHI ALSTTLs M 74A LS191P SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER W ITH MODE CONTROL • 7 ^ V ' 5 ' ' ^ >3 DESCRIPTION - o 7 PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 9 1 P is a s e m ic o n d u c to r in te g ra te d c irc u it