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    74AC11086DR Search Results

    74AC11086DR Datasheets (8)

    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    74AC11086DR
    Texas Instruments Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85 Original PDF 426.89KB 10
    74AC11086DR
    Texas Instruments Quadruple 2-Input Exclusive-OR Gates Original PDF 250.49KB 8
    74AC11086DR
    Texas Instruments 74AC11086 - Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85 Original PDF 224.61KB 9
    74AC11086DRE4
    Texas Instruments Quadruple 2-Input Exclusive-OR Gates Original PDF 261.73KB 8
    74AC11086DRE4
    Texas Instruments Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85 Original PDF 426.89KB 10
    74AC11086DRE4
    Texas Instruments 74AC11086 - Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85 Original PDF 224.61KB 9
    74AC11086DRG4
    Texas Instruments Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85 Original PDF 426.89KB 10
    74AC11086DRG4
    Texas Instruments 74AC11086 - Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85 Original PDF 224.61KB 9
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    74AC11086DR Price and Stock

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    Texas Instruments 74AC11086DR

    IC GATE XOR 4CH 2-INP 16SOIC
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    DigiKey 74AC11086DR Reel 2,500
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    Verical 74AC11086DR 5,000 224
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    Rochester Electronics 74AC11086DR 5,000 1
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    Rochester Electronics LLC 74AC11086DR

    IC GATE XOR 4CH 2-INP 16SOIC
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    DigiKey 74AC11086DR Bulk 205
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    Texas Instruments 74AC11086D

    Logic Gates Quad 2-Input
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    Mouser Electronics 74AC11086D 534
    • 1 $2.87
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    Texas Instruments 74AC11086DRG4

    Peripheral ICs
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    Vyrian 74AC11086DRG4 1,622
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    Texas Instruments SN74AC11086DR

    Peripheral ICs
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    Vyrian SN74AC11086DR 302
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    74AC11086DR Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil 4-Oct-2007 74AC11086DR PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil 9-Jun-2007 74AC11086DR 74AC11086DR PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil PDF

    74AC11086

    Abstract: 74AC11086D 74AC11086DE4 74AC11086DR 74AC11086DRE4 74AC11086N
    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil 74AC11086 74AC11086D 74AC11086DE4 74AC11086DR 74AC11086DRE4 74AC11086N PDF

    74AC11086

    Abstract: 74AC11086D 74AC11086DE4 74AC11086DG4 74AC11086DR 74AC11086DRE4 74AC11086DRG4 74AC11086N 74AC11086NE4
    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil 19-Mar-2008 74AC11086DR 74AC11086 74AC11086D 74AC11086DE4 74AC11086DG4 74AC11086DR 74AC11086DRE4 74AC11086DRG4 74AC11086N 74AC11086NE4 PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil 12-Jan-2008 74AC11086DR PDF

    74AC11086

    Abstract: 74AC11086D 74AC11086DR 74AC11086N
    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil 74AC11086 74AC11086D 74AC11086DR 74AC11086N PDF

    Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at


    Original
    74AC11086 SCAS081A 500-mA 300-mil PDF