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74AC11086DE4 Datasheets (3)

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Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
74AC11086DE4		Texas Instruments	Quadruple 2-Input Exclusive-OR Gates	Original	PDF	261.73KB	8
74AC11086DE4		Texas Instruments	Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85	Original	PDF	426.89KB	10
74AC11086DE4		Texas Instruments	74AC11086 - Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85	Original	PDF	224.61KB	9

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Texas Instruments


Texas Instruments 74AC11086DE4 XOR Gate, AC Series, 4-Func, 2-Input, CMOS, PDSO16
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	74AC11086DE4		4,751			1 - 10 - 100 - 1000 - 10000 -	Get Quote

74AC11086DE4 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil +24-oct-2007 74ac11086dr	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil +29-jun-2007 74ac11086dr	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil	PDF
74AC11086 Abstract: 74AC11086D 74AC11086DE4 74AC11086DR 74AC11086DRE4 74AC11086N Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil +574ac11086d 74ac11086de4 74ac11086dr 74ac11086dre4 74ac11086n	PDF
74AC11086 Abstract: 74AC11086D 74AC11086DE4 74AC11086DG4 74AC11086DR 74AC11086DRE4 74AC11086DRG4 74AC11086N 74AC11086NE4 Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil +919-mar-2008 74ac11086dr 74ac11086d 74ac11086de4 74ac11086dg4 74ac11086dre4 74ac11086drg4 74ac11086n 74ac11086ne4	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil +212-jan-2008 74ac11086dr	PDF
Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 500-mA Typical Latch-Up Immunity at	Original	74ac11086 scas081a 500-ma 300-mil	PDF