74LS5 Search Results

74ls597

Abstract: 74LS59B
Contextual Info: SN54LS597, SN 54LS598, 74LS597. SN 74LS59B 8 BIT SHIFT REGISTERS WITH INPUT LATCHES 02635 8-Bit Parallel Storage Register Inputs 'LS597J JA N U A R Y 1981 - REVISED M AR C H 1988 S N 5 4 L S 5 9 7 . . . J OR W P AC KA G E S N 7 4 L S 5 9 7 . . . N P AC KA G E

74LS PINOUT

Abstract: 74H54FC 74LS54PC 7454DC 7454FC 7454PC 74H54DC 74H54PC 74LS54DC 74LS54FC
Contextual Info: 54 C O N N E C T IO N D IA G R A M S P IN O U T A Vm /7454 ^54H/74H54^ 54LS/74LS54 ^ 4-W IDE, 2-IN PU T AND-O R -IN VER T GATE O R D E R IN G CO D E: See S e c tio n 9 PIN PKGS P la stic D IP P C O M M E R C IA L GRADE M IL IT A R Y G RADE V cc = +5.0 V ±5%,

4 inputs OR gate truth table

Abstract: 74LS55 751A-02 4 inputs OR gate datasheet SN54LSXXJ SN74LSXXN SN74LSXXD truth table NOT gate 74
Contextual Info: SN54/74LS55 2-WIDE 4-INPUT AND-OR-INVERT GATE 2-WIDE 4-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 1 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

74LS55

Abstract: 751A-02
Contextual Info: SN54/74LS55 2-WIDE 4-INPUT AND-OR-INVERT GATE 2-WIDE 4-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 1 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

D flip-flop 74175 pin

Abstract: 74LS78 74LS374 74ls373 93L38 74298 D150 D190 74LS374 74LS373 74ls373 D Flip-Flop
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 Vcc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| FI j j j SD SD J Q J C CP Q — e CP K >— 12 Q Q 5— 9 K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 li 5 D85 54LS/74LS373

74LS93 P

Abstract: TTL 74LS93 74293 pin diagram 74LS78 TTL 74293 74176 74293 74LS490 74LS93 74LS373
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| FI j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 li 5 D85

K D S 4L

Abstract: ttl 74LS173 ttl 74165 ttl 74166 74ls399 93L38 74170 74LS165 TTL 74ls195 54LS
Contextual Info: FAIRCHILD DIGITAL TTL 54LS 3 74LS574 8 8S P a ra lle l-in /S e ria l-o u t 54/7494 4 D 4S 4 P a ra lle l-in /S e ria l-o u t 54/74165 8 D 8A 35 20 37 D96 _r 55 20 135 D97 9Z 10 25 175 D165 4L,7B,9B 26 19 210 D175 4L,7B,9B 35 20 360 D176 4L,7B,9B 40 19 105

74122

Abstract: 74LS568 TTL 74121 ttl 7497 54LS 96L02 96LS02 96S02 D187 D188
Contextual Info: FAIRCHILD DIGITAL TTL U p/D o w n 54LS 2,/74LS568 Presettable 16 L o g ic /C o n n e c tio n D ia g ra m Power D issipation s s J- _ _ _ D99 9Z 32 20 400 D187' 4L,7B,9B 32 20 325 D188 4L,7B,9B 54LS(2 /74LS569 3 Rate M u ltip lie r 54/7497 M.f./64 — 4 Rate M u ltip lie r

LS373

Abstract: 74LS573 "LATCH" 74LS573DC 74LS573PC 74LS573 LATCH 54LS573DM 54LS573FM 74LS573FC 74*573 "LATCH" 54LS573
Contextual Info: 573 CONNECTION DIAGRAM PINOUT A 54LS/74LS573 Of H 5 OCTAL D-TYPE LATCH ere [7 With 3-State Outputs d o [T D, DESCRIPTION — The ’573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. 2ÖJ Vcc

7451 ic

Abstract: 54S51 74LS51 74H51PC
Contextual Info: 51 CO NNECTIO N DIAGRAMS PINOUT A Offo-pfa 1/^4/7451 v^4H /74H 51 r -h M i S4S/74S51 ' - ’ ^Ö4LS/74LS51 m h ò ' f DUAL 2-WIDE, 2-INPUT AOI GATE DUAL 2-WIDE, 2-INPUT/3-INPUT AOI GATE CLS51 ORDERING CODE: See Section 9 PIN PKGS Plastic DIP P) Ceramic DIP (D)

74LS502

Contextual Info: 502 CO NNECTIO N DIAGRAM PINOUT A 0 ( ( Q^ 54LS/74LS502 8-BIT SUCCESSIVE APPROXIMATION REGISTER D E SC R IPTIO N — The 'LS502 is an 8-bit register w ith the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Com plete (CC signal coincident with storage o f the eighth

Contextual Info: LS51 National JCm Sem iconductor 54LS51/DM 74LS51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gates General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function. Each package contains one 2-wide 2-input and

74LS54

Abstract: 751A-02
Contextual Info: M MOTOROLA. SN54/74LS54 3-2-2-3-INPUT AND-OR-INVERT GATE 3-2-2-3-IN PU T A N D -O R -IN V E R T GATE LOW POWER SCHOTTKY Vcc J SUFFIX CERAMIC CASE 632-08 N SUFFIX PLASTIC CASE 646-06 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD

CI 7401

Abstract: N7451F 7451 pin configuration 74H51 74LS N7451N N74H51F N74H51N N74LS51F N74LS51N
Contextual Info: PIN CONFIGURATIONS 5 4 /7 4 5 1 54H /74H 51 54S/74S51 54LS/74LS51 ORDERING CODE See Section 9 fo r further P ackage and Ordering Inform ation COMMERCIAL RANGES MILITARY RANGES V C C = 5 V ± 5 % ; T a = 0°C t o + 7 0 °C V C C = 5 V ± 1 0 % ; T A = —5 5°C t o + 1 2 5 °C

74ls gate symbols

Abstract: 74LS54 74LS N74LS54D N74LS54N
Contextual Info: 74LS54 Signetics Gate Four-Wide Two- & Three-Input AND-OR-lnvert Gate Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 1 2 ns 0.9mA 74LS54 ORDERING CODE COMMERCIAL RANGE VCC = 5 V ± 5 % ; T * = 0°c to +70°C

74LS534

Abstract: SN74LS534N 74LS53 74LS SN74LS534 4LS374 SN74LS374AN
Contextual Info: Am25LS374A • Am54LS/74LS374A Am25LS534 • Am54LS/74LS534 8-Bit Registers with Three-State Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • 8-bit, high-speed parallel registers • Positive, edge-triggered, D-type flip-flops • Buffered common clock and buffered common three-state

74LS55

Contextual Info: g MOTOROLA SN54/74LS55 2-WIDE 4-INPUT AND-OR-INVERT GATE 2-WIDE 4-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY Vcc rrn nn nii rrn ftoi in rn J SUFFIX CERAMIC CASE 632-08 14 LU LU LiJ LU L±J Ll I Lj J 1 GND N SUFFIX PLASTIC CASE 646-06 & D SUFFIX SOIC 5

Contextual Info: <8 > M O T O R O L A SN54/74LS569A FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS The SN54/74LS569A is designed as programmable up/down BCD and Binary counters respectively. These devices have 3-state outputs for use in bus organized systems. With the exception of output enable OE and

Contextual Info: g M O T O R O L A D E S C R IP T IO N — The S N 54LS/74LS540an d SN54LS/74LS541 are octal buffers and line drivers with the same functions a s the LS240and LS241. but with pinouts on the opposite side of the package. These device types are designed to be used as memory address drivers,

74LS55

Contextual Info: g M O TO R O LA SN54/74LS55 2-WIDE 4-INPUT AND- OR-INVERT GATE U U U T iJ LULl T'LI LOW POWER SCHOTTKY J Suffix — Case 632-08 (Ceramic) N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES S YM B O L MIN TYP MAX UNIT VCC Supply Voltage PARAMETER

74LS51 truth table

Abstract: 74LS51
Contextual Info: g MOTOROLA SN54/74LS51 £ lR R E L a M £ l DUAL 2-WIDE 2-INPUT/ 3-INPUT AND-OR-INVERT GATE □ LU LU LU Lü LU LU LOW PO W ER SCH O T TK Y J Suffix — Case 632'08 (Ceramic) N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES MIN TYP . MAX UNIT

SN74LS573

Contextual Info: Advance Information SN54LS573/74LS573 OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS G EN E R A L DESCRIPTION - The 54LS/74LS573 is a High-Speed Octal Latch with Buffered Common Latch Enable LE and Buffered Common Output Enable (OE) inputs. This device is functionally identical to the 54LS/74LS373, but has different pin­

Contextual Info: 574 ' 54LS/74LS574 oil (A CONNECTION DIAGRAM PINOUT A OCTAL D-TYPE FLIP-FLOP (With 3-State Outputs DESCRIPTION — The '574 is a high speed low power octal flip -flo p w ith a buffered com m on Clock (CP) and a buffered com m on O utput Enable (OB. The inform ation presented to the D inputs is stored in the flip -flop s on the

Contextual Info: 573 CONNECTION DIAGRAM / / PIN O U T A 0 !7/^3 54LS/74LS573 O C T A L D - T Y P E L A T C 2 o] V c c o e |T H With 3-State Outputs do Q[ U o o d ,|T i3 ] o i D2 [7 DESCRIPTION — The '573 is a high speed octal latch with buffered common d3[? l| ] 0 3 d4[7