74LS14 Search Results

DN74LS145

Contextual Info: LS TTL DN74LS Series 74LS145 74LS145 iv ^ L S ^ BCD to Decimal Decoders / Drivers P-2 • Description DN 74LS145 is a BCD to decim al decoder/ driver w ith open collector o u tp u ts. ■ Features • • • • Large o u tp u t cu rrent I o l ^ 80m A m axim um )

74LS14PC

Abstract: 7414PC PIN OUT 74LS14 pin diagram of 7414 74LS14 5414DM schmitt trigger 7414 74LS14DC 7414DC 7414
Contextual Info: 14 CON NECTIO N DIAG RAM PINO UT A 54/7414 r '''54LS/74LS14 ¿v/ ' 7/ HEX SC HM ITT TRIGGER INVERTER I ORDERING CODE: See Section 9 PIN PKGS OUT Plastic DIP P A Ceramic DIP (D) A COMMERCIAL GRADE V cc = +5.0 V ±5%, T a = 0 °C to +70° C MILITARY GRADE

Contextual Info: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which performs the logic INVERT function. Each in­ put has hysteresis which increases the noise im­ munity and transforms a slowly changing input signal

Contextual Info: GD54/74LS145 BCD-TO-DECIMAL DECODER/DRIVER Features Pin Configuration • Full Decoding of Input Logic • 80-m A Sink-Current Capability • All Outputs Are Off for Invalid BCD Input Con­ ditions • Low Power Dissipation of ’L S 1 4 5 .3 5 mW Typical

74LS147

Abstract: 74ls147 pin diagram FUNCTIONAL APPLICATION OF 74LS148 74ls148 74LS147 equivalent motorola 74ls147 74ls748 SN54/74LS147 FAST AND LS TTL ls74
Contextual Info: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are

TOP 242 PN

Abstract: TTL 74145 LS 74145 74LS145 SN74LSXXXD SN74LSXXXN SN54LSXXXJ 751B-03
Contextual Info: SN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR The SN54 / 74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is

SN7414

Abstract: sn7414 circuit SN414
Contextual Info: SN5414, SN54LS14, SN7414, 74LS14 HEX SCHMITT-TRIGGER INVERTERS D ECEM BER 1 9 8 3 -R E V IS E D MARCH 1988 Operation from Very Slow Edges SN&414, SN 54LS14 J OR W PACKAGE S N 7414 . . . N PACKAGE SN 74LS14 . D OR N PACKAGE • Improved Line-Receiving Characteris­

Contextual Info: • 8 -Nne-to-3-line Octal Priority Encoders IBLOCK DIAGRAM The H D 74LS148 encodes eight data lines to three-line 4-2-1 binary (octal). Cascading circuitry (enable input El and enable output EO) has been provided to allow octal expansion w ith ­ out the need for external circuitry. The data inputs and out­

pin diagram of ic 74ls148

Contextual Info: GD54/74LS148 8-TO-3 LINE PRIORITY ENCODER Features Pin Configuration • Priority Decoding of the Data Inputs • • • Code conversions Decimal-to-BCD Converter Group Serial Output active when any input is low VCc OUTPUT ENABLE EÖ GS 55 d3 d2 D, D5 Do

74LS14 oscillator 4 Mhz

Abstract: 74ls14 pin configuration 74LS14 function table pin configuration 74LS14 74ls14 ttl 74ls14 74LS TTL Oscillator 54LS 74LS IN3064
Contextual Info: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which performs the logic INVERT function. Each in­ put has hysteresis which increases the noise im­ munity and transforms a slowly changing input signal

IC 74LS14

Abstract: 74ls14 74LSxx ic 74ls13
Contextual Info: M OTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The S N 54LS /74LS 13 and SN 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

74LS145

Contextual Info: <8> M OTOROLA SN54/74LS145 DESCRIPTION — T h e S N 5 4 L S / 7 4 L S 1 4 5 ,1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit in candescent displays- A ll outputs rem ain off for all invalid binary input conditions. It is designed for use as in dicator/relay drivers

LS748

Abstract: 74LS147 74LS148 74lS748
Contextual Info: g MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the SN 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order

74ls145

Abstract: 74LS145DC Q912 74LS145 equivalent SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR The SN54 / 74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is

biffi

Contextual Info: DËj| tiTBSñSE OODVCmt, 7 | ~ 6 93 2 8 52 P ANASONI C INDL» ELECTRONIC LS TTL D N 74L S 5>U —X _ _ PANASONIC INDL/ELEK -CIO 72 ' 72C 0 7 0 4 6 P.T-66-21-57 dn 74LS148/ dn 74LS148S D N 7 4 L S 14 8 /D N 7 4 L S 1 4 8 S 8 -lin e to 3-lin e Octal P r io r ity Encoders

74LS14 not gate

Abstract: 74LS14 74ls14 ttl ttl 74ls14 74LS14 DATA LS14 74LS13 TTL Schmitt-Trigger Inverters 751A-02 LS13
Contextual Info: MOTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN 54LS /74LS 13 and S N 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

74LS147

Abstract: 74LS148 PIN 74LS147
Contextual Info: M MOTOROLA D ESCRIPTIO N — The S N 5 4 L S /7 4 L S 147 and th e S N 54 L S /7 4 L S 148 SN54LS/74LS147 SN54LS/74LS148 SN54LS/74LS748 are Priority Encoders. They provide prio rity decoding of the inputs to ensure th a t only th e highest order data line is encoded. Both devices

IC 74LS14

Abstract: IC TTL 74 ls 04 ic 74ls13 74LS14
Contextual Info: fò MOTOROLA SN54/74LS13 SN54/74LS14 D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 1 3 and S N 5 4 L S /7 4 L S 1 4 c o n ta in logic g ate s/in v erters w h ic h accept standard TTL input sig n a ls and provide standard TTL output levels. They are capable o f transform ing

74LS145

Abstract: TS02H
Contextual Info: fQ MOTOROLA SN54/74LS145 1-OF-IO DECODER/DRIVER OPEN-COLLECTOR The S N 54/74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is

74LS147

Abstract: 74LS148 74ls748 LS748 PIN 74LS147 LS148 ttl 74ls147 LS 74LS147 6200S ttl 74ls148
Contextual Info: <8 > MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the S N 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order

ttl 74ls14

Contextual Info: MOTOROLA SN54LS/74LS13 SN54LS/74LS14 D E S C R IP T IO N — The S N 54 L S /7 4 L S 1 3 and S N 54 L S /7 4 L S 14 co n ta in logic g ate s/inve rte rs w hich accept standard TTL input signals and provide standard TTL output levels. They are capable of transform ing

74LS14 not gate

Abstract: 74LS14 ttl 74ls14 74ls13 74ls14 ttl equivalent for 74LS13 TTL Schmitt-Trigger Inverters TTL Schmitt-Trigger LOW POWER SCHOTTKY 74 LS 14 Logic Gates 74LS14 datasheet
Contextual Info: SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

74LS00 7400 74S00

Abstract: 74LS04 74LS04 NOT gate 74LS00 74LSoo 74H04 74H00 TTL 74ls00 TTL 7404 TTL 74ls04
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,

IC 7404 7406

Abstract: 74LS00 7400 74S00 IC TTL 74LS00 ic 7404 74LS04 Hex Inverter Gates ic 74132 TTL 74h04 Fairchild 9002 ic 7404 fairchild 74LS132
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,