74HC138 Search Results

CD74HC138MT

Abstract: CD74HC138M96E4 74HC138
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

CD74HCT138/238

Contextual Info: Technical Data File N um b er CD54/74HC138, CD54/74HCT138 CD54/74HC238, CD54/74HCT238 1477 HARRIS SEMICOND SECTOR 57E D B 4302E71 DQlTSTh 0 « H A S High-Speed CMOS Logic H C /H C T H C /H C T 238 138 m -v o d f i i ; 12 Y3 - l i — Y4 - y - v s Y6 — — Y7

C6093

Abstract: 74HC138A HC138A ADI1455 HC138 LS138 MC54HCXXXAJ MC74HCXXXAD MC74HCXXXAN
Contextual Info: Order this data sheet by M C54/74HC138A/D MOTOROLA S E M IC O N D U C TO R TECHNICAL DATA MC54/74HC138A Advanced Information J SUFFIX CERAMIC CASE 620-09 1 -o f- 8 D e c o d e r /D e m u ltip le x e r H ig h -P erfo rm a n ce S ilic o n -G a te C M O S N SUFFIX

74HC14D

Abstract: TC74HCT14 74hc595d TC74HCT14AF NXP 74HC14D 74HCT04D 74HCT14PW 74HC125DR2G 74HC14D-T 74HCT14D
Contextual Info: ON SEMI 74HC00DR2G 74HC00DTR2G 74HC02DR2G 74HC02DTR2G 74HC04DR2G 74HC04DTR2G 74HC08DR2G 74HC08DTR2G 74HC125DR2G 74HC125DTR2G 74HC132DR2G 74HC132DTR2G 74HC138DR2G 74HC138DTR2G 74HC14DR2G 74HC14DTR2G 74HC244DTR2G 74HC245DTR2G 74HC32DR2G 74HC32DTR2G 74HC373DTR2G

diagram of LED matrix using 4017

Abstract: 4017-DECADE COUNTER ic 4017 decade counter datasheet ic 4017 IRFZ44 mosfet for square wave inverter IRFZ44 mosfet 4017 COUNTER IC ic 4017 PIN DIAGRAM LM1458 pin configuration 2N3055 inverter schematic diagram
Contextual Info: 16 Stage Bi-Directional LED Sequencer The bi-directional sequencer uses a 4 bit binary up/down counter CD4516 and two "1 of 8 line decoders" (74HC138 or 74HCT138) to generate the popular "Night Rider" display. A Schmitt Trigger oscillator provides the clock signal for the counter and the rate can be adjusted with the

74HC138

Abstract: 74HC138 using for testing equipment CD74HC138M96 74HC138 using for medical equipment
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

74HC138

Abstract: CD74HC138M96 CD54HC138F3A CD54HC238F3A CD54HCT138F3A CD54HCT238F3A CD74HC138E CD74HC138M
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

HC238

Abstract: 74HC138 74HCT238 HC138 HCT138 HCT238
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147F October 1997 - Revised May 2003 High-Speed CMOS Logic 3- to 8-Line Decoder/

Contextual Info: Technical Data File N u m b e r CD54/74HC138, CD54/74HCT138 CD54/74HC238, CD54/74HCT238 1477 High-Speed CMOS Logic H C /H C T H C /H C T 138 3-to-8 Line Decoder/Demultiplexer Inverting and Non-Inverting Type Features: • S e le c t o n e o f e i g h t d at a o u t p u t [ ac tive L O W f o r 138,

74HC_HCT138

Abstract: 74HC138 data sheet 74HC138 EQUIVALENT 74HCT138 74HC138DB 74HC138N hct138d 74HC138 philips 74HCT138 74HC138PW
Contextual Info: 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 03 — 23 December 2005 Product data sheet 1. General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1

74HC138AD

Abstract: 74HC138A 74HC138
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1 -o f-8 Decoder/D em ultiplexer M C54/74HC138A High-Performance Silicon-Gate CMOS The M C54/74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors,

hj238

Abstract: HCT238M
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

74HC138

Abstract: HCT238 harris CD74HC138MT CD74HC138M96E4 CD54HC138F3A CD54HC238F3A CD54HCT138F3A CD54HCT238F3A CD74HC138E CD74HC138M
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

74HC138A

Abstract: HC138A
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1 -of-8 Decoder/Dem ultiplexer MC54/74HC138A High-Performance Silicon-Gate CMOS The MC54/74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard C M O S outputs; with pullup resistors,

74HC138

Abstract: hct138d 74HC138D HCT138 74HC138 philips 74HC138DB 74HC138N 74HC138PW 74HCT138 74HCT138N
Contextual Info: 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Product data sheet 1. General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1

PC 74HC138

Abstract: ic 74HC138 HC138 74HC138 74HC238 74HCT238 74hc138 harris CD54HC138F3A CD54HCT138F CD74HC138M
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147C October 1997 - Revised August 2001 High Speed CMOS Logic 3-to-8 Line Decoder/

74HC138

Abstract: 74HC138DR HC138G 74HC138D 74HC138DR2G 74HC138DTR2G D74HC138 HC138 948F LS138
Contextual Info: 74HC138 1−of−8 Decoder/ Demultiplexer High−Performance Silicon−Gate CMOS The 74HC138 is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138 decodes a three−bit Address to one−of−eight active−low

74HC138 using for testing equipment

Abstract: MNA370 DHVQFN16 SOT763-1 74HC138 74HCT138 74LV138 74LV138BQ 74LV138D 74LV138DB
Contextual Info: 74LV138 3-to-8 line decoder/demultiplexer; inverting Rev. 03 — 15 November 2007 Product data sheet 1. General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted

74HC138

Abstract: related circuit of 74HC138 001aae059 74HC-HCT138 74hc138bq hct138 74HC138 using for testing equipment 74HC138D 74HC138N 74HC138DB
Contextual Info: 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 4 — 27 June 2012 Product data sheet 1. General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1

74HC138

Abstract: HC138 74HCT238 74HCT13 CD54HC138F3A CD54HC238F3A CD54HCT138F3A CD54HCT238F3A CD74HC138E CD74HC138M
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147H October 1997 - Revised May 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

74HC138

Abstract: CD74HC138M96 CD74HC138MT CD54HC138F3A CD54HC238F3A CD54HCT138F3A CD54HCT238F3A CD74HC138E CD74HC138M
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

74HC138

Abstract: GD74HCT138 74HCT138 GD54HC138 GD74HC138 74HC 74ls138 demultiplexer
Contextual Info: GD54/74HC138, GD54/74HCT138 3-TO-8 LINE DECODER/DEMULTIPLEXER General Description Pin Configuration These devices are identical in pinout to the 5 4 /7 4 L S 1 3 8 . Each device has 3 Binary select A, B, and C , and decodes A 3-Bit address to 1 -of-8 active-LOW outputs. This device features three chip

54HC138

Abstract: 74HCT238E 74HC138 74HCT238 ic 74HC138 74HC138 P CD74HCT138 74HC138C
Contextual Info: _ Technical Data File N um ber CD54/74HC138, CD54/74HCT138 CD54/74HC238, CD54/74HCT238 1477 High-Speed CMOS Logic H C /H C T H C /H C T 138 3-to-8 Line Decoder/Demultiplexer Inverting and Non-Inverting T y p e Featu res: Y5 Ÿ6 Y7 • S elect one o f eig h t data o u tp u t [active LO W fo r 138,