7417 Search Results

ic 7407

Abstract: IC 7417 specifications ic 7407 2yl1 7407 7417 TTL
Contextual Info: TYPES SN5407, SN5417, SN7407, 7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS _ Converts TTL Voltage Levels to MOS Levels R E V IS E D D E C E M B E R 1 9 8 3 S N 5407, S N 5417 . . . J OR W PACKAGE S N 7407, S N 7417 . . . J OR N PACKAGE

74L5

Contextual Info: TYPES SN54173, SN54LS173A, 74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS OCTOBER 1976 — REVISED APRIL 1985 S N 54173, SN 54LS 173A . . . J OR W PACKAGE S N 7417 3 . . . J OR N PACKAGE S N 74L5 173A . . . D, J OR N PACKAGE 3-State Outputs Interface Directly w ith

IC 74173

Abstract: ttl 74173 74173 ic ap 5331 8T10 74173 74173+truth+table
Contextual Info: Signelics 74173, LS173 Flip-Flops Quad D-Type Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES • Edge-triggered D-type register • Gated input enable for hold "do nothing" mode • 3-State output buffers • Gated output enable control

74177

Abstract: pin diagram of 177 74177PC 54177DM 54177FM 74177DC 74177FC
Contextual Info: 1 7 7 C O N N E C T IO N D IA G R A M P IN O U T A '54/74177 ¿>/ 0 s_ss PRESETTABLE BINARY C O U N T E R PL T 14] Vcc 02 (T 1^ MR p2 12] 03 £ [ po[ T 11] P3 Qo| T j o ] Pi c p i[ T 7 ] a, g nd D E S C R IP T IO N — T he'177 is a p re se tta b le m o d u lo -1 6 rip p le c o u n te r p a rti­

74174PC

Abstract: 74LS174PC 74LS174P 74174DC 74174FC 74LS174DC 74LS174FC 74S174DC 74S174FC 74S174PC
Contextual Info: 174 CONNECTIO N DIAGRAM PINOUT A 4/74174 54S /74S174 q 54LS/74LS174 \J a i / c c r-\ » mr[T 16] Vcc ïïla s Qo T HEX D FLIP-FLO P |T if] Ds t>i | T Î3ID4 d o Qi [7 12] Ds [6 T flP 3 Q îfT 101 0 3 g n d Q4 ~n cp [T DESCRIPTION — T h e ’17 4 is a high sp eed hex D flip -flo p . T h e d e vice is

7417PC

Abstract: SDF17N60 5417DM 5417FM 7417DC 7417FC
Contextual Info: 17 C O N N E C T IO N D IA G R A M P IN O U T A 54/7417 e ì t-i- ^ HEX BUFFER/DRIVER W ith O p e n -C o lle cto r H ig h-V oltage Output E E E E EZ E O R D E R IN G C O DE: See S e c tio n 9 PIN PKGS C O M M E R C IA L G R A D E V c c = +5 .0 V ±5%, T a = 0° C to + 7 0° C

74176

Abstract: BCD 8421 74176DC 54176DM 54176FM 74176FC pin diagram decade counter 74176 T-13-L
Contextual Info: 176 C O N N E C T IO N D IA G R A M P IN O U T A '54/74176 b/ 0 £ > 3 < / PR ESETTA B LE D E C A D E C O U N T E R pi. [T 14| Vcc 02 |T Î 3 l MR P2 IT 12] 03 P o [T ÏT| p3 Qo|T 10] Pi c p i| T T ]Q r G ND [ 7 D E S C R IP T IO N — The ’176 is a presettable decade ripple counter partitioned

74174

Abstract: 74175 74273
Contextual Info: — 142 — 74174 HEX D-FFs [ r - s C Ir trs -ö > IQ s — íp «4 >CK H *CK CHAH U iü J — J— — !— CLiM CLCAR CK< » * >CK J L \ 7 ? Î - 1 CLEAN lJJT±JTÌJTjJT_5JT_ _rLj_rLì_r^ 10 07474 9 4-f 'J -Ti Î0 > / x v ¿> » \ ' n JO 30 ONO

74398

Abstract: 74157 74175 74399
Contextual Info: — 19 6 74298 4-B it 2 Input Multiplex Register Vcc Oa Qb Oc o p C LO C K S ELE CT C1 niriiiiijiAJiiJiiJLüur , B2 A2 Al Bì C2 V D A TA INPUTS 74157i 74175£ 74399i 02 DI GND 9 4 7" Ü 7 o v ms ±'\' At A Word L H N LS fmax n CLK 25 25 100 tw n CLK 20 20

74157 pin diagram

Abstract: TTL 74153 74s157 pin diagram fairchild 9312 74157 D157 Fairchild 9322 93L09 74S153 93L22
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL - T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 15 H 1 2 3 12 11 10 I M Ew Ü2 Dl D3 loa I la 1 3 - W b 1 3 - So 5 - Ra 3 - S i N T 14 11 10 6 T 7 E lo 11 3 3 5 6 S 11— 0 CP 7 lOb 11b lOc l i e

74691

Abstract: 74257 74691 counter 74175 BA RV O74160-74163
Contextual Info: - 298- Binary Synchronous Counters 74691 3 STATE OUTPUTS vcc output Qa Ob oc jii-H -jTL-f » oo t I öä O. G s tu KU-» 1J« U L is s ü J lir Û lli 1LÎ llf ‘-Li llT iir - ir DAf A INPUTS ENABLE AEGlST BEGISi fH ER t m i CLOCK 0 74160—741631-74175, 74257

OF IC 74170

Abstract: 54170FM
Contextual Info: 170 CO NNECTIO N DIAGRAM PINOUT A 1/54/74170 54LS /74LS 170 11 0 / , ~i ^ T— r 4 X 4 REGISTER FILE With O pen-Collector Outputs DE S C R IP TIO N — The ’170 contains 16 high speed, low power, transparent D-type latches arranged as four words of fou r bits each, to fun ctio n as a

74LS170N

Abstract: OF IC 74170 74170 FA 5323
Contextual Info: 74170, LS170 Signetics Register Files 4 x 4 Register File Open Collector Product Specification Logic Products FEATURES • Simultaneous and independent Read and Write operations • Expandable to 1024 words by n-bits • Open Collector outputs for wiredAND expansion

Contextual Info: 176 CO NNECTIO N DIAGRAM PINOUT A ' 54/74176 fr/ PRESETTABLE DECADE COUNTER [7 14| V cc Q2 [7 13] MR PL p2 [7 Ü ] 03 po[ T Ï T | p3 Oo[T ÎÔ ]P l 7 ] Or C P i T G ND [7 DESCRIPTION — The ’176 is a presettable decade ripple counter partitioned into divide-by-tw o and divide-by-five sections, w ith separate clock inputs for

74173

Abstract: DM8551 74173 pin configuration 8T10 ttl 74173 ttl 74LS173 74LS 74LS173 CD7186D N74173N
Contextual Info: SigneHcs 74173, LS173 Flip-Flops Quad D-Type Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES • Edge-triggered D-type register • Gated Input enable for hold "do nothing" mode • 3-State output buffers • Gated output enable control

SN74112

Abstract: SN74172 1972-REVISED register file L817
Contextual Info: 74172 16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS MAY 1972—REVISED MARCH 1988 SN 74172 . . . N PACKAGE Independent Read/Write Addressing Permits Simultaneous Reading and Writing • T O P V IE W 1W 1 C 1 L ^ 2 4 D v c c 23 Ü 1 W 2 1W 0 C 2

D flip-flop 74175 pin data sheet

Abstract: IC 74175 SN74175N quad D flip-flop 74175 pin data sheet 7400 fan-out 7400 signetics 74175 pin data sheet quad D flip-flop 74175 pin 74174 data sheet IC 7400
Contextual Info: o ii5 S ,9 Am54/74174* Am54/74175 H ex/Q uadruple D-Type Flip-Flops with C lear Distinctive Characteristics \ Buffered clock and direct clear inputs. • • i Individual data input to each flip-flop. 35 M H z ty p ic a l c lo c k frequency. 100% r e lia b ility assurance testincj in com p lia n ce w ith

transistor 702

Abstract: 74148 74172
Contextual Info: 45,0 L .453 Ø 11,5 1.77 binder S T E C K V E R B I N D E R Serie Series 702 franz binder gmbh + co. elektrische bauelemente kg postf. 1152 • 74148 neckarsulm rötelstr. 27 · 74172 neckarsulm telefon +49 0 71 32/325 - 0 telefax +49 (0) 71 32/325 - 150

74179

Abstract: 74178 ttl 74178 ScansUX986
Contextual Info: TTL/MSI 93178/54178, 74178 93179/54179, 74179 4-BIT SHIFT REGISTERS -! B F AN N O U N CED D E S C R IP T IO N — The 9 3 1 7 8 and 9 3 1 7 9 are 4 -B it S h ift Registers w ith b o th serial and pa rallel data e n try c a p a b ility . The 9 3 1 7 9 features a d ire c t reset

74174PC

Abstract: 74174
Contextual Info: NATIONAL SEMICOND -ELOGIO OPE D | bSDllSB üüb3öfl4 3 | 174 T -4 6 -0 7 -1 0 CO NNECTIO N DIAGRAM PINOUT A 54/74174 54S /74S 174 54LS /74LS 174 1 HEX D FLIP-FLOP DESCRIPTION — The '174 is a high speed hex D flip -flo p. The device is used prim arily as a 6-bit edge-triggered storage register. The inform ation

pin DIAGRAM OF IC 74

Abstract: 74176PC
Contextual Info: NATIONAL SEflICOND -CLOCIO G2E D 176 I b s o iiE e 0 0 ^3 0 ^ 0 ^ I -•! 3 _ T- CO NN ECTIO N DIAGRAM PINOUT A 54/74176 PRESETTABLE DECADE COUNTER D E S C R IP T IO N — The '176 is a presettable decade ripple counter partitioned into divide-by-two and divide-by-five sections, with separate clock inputs for

OF IC 74170

Abstract: 4LS170 ic 74170 74170
Contextual Info: 7 4 1 7 0 , LS1 7 0 Register Files S ig n e t ic s 4 x 4 Register File Open Collector Product Specification Logic Products FEATURES TYPICAL PROPAGATION DELAY (RE to Q) TYPICAL SUPPLY CURRENT (TOTAL) 74170 10ns (tPLH) 20ns (tpHL) 127mA 7 4LS170 20ns (tPLH)

Contextual Info: 361-060-0040H 8EV A RELEASED PER ECR 7417 Ï .530 [13.46] .100 [2.54] TYP. .155 [3.94] .375 [9.53] 0.050 [01.27] 0.300 June 2006 - This drawing became the property of Winchester Electronics Corporation, Wallingford, CT. .040 [1.02] SQ. TYP. ¥ >r OMl •

IC 74175

Abstract: H1322 sylvania logic
Contextual Info: Sylvania ECG Sem ico nd ucto rs 74174, LS174, S174, 74175, LS175, S175 Hex/Quad D Flip-Flops with Clear These positive-edge-triggered flip-flop s u tilize T T L c irc u itry to im plem ent D t y p e flip -flo p logic. A ll have a d ire ct clear in p u t, and the quad 1 7 5 versions feature