74 LS 18 Search Results

Contextual Info: SN54ALS168B, SN54ALS169B, SN54AS168, SN54AS169 S N 74 A LS 16 8 B , S N 74 A LS 16 9 B , S N 74 A S 16 8 , S N 74AS16 9 SYNCHRONOUS 4-BIT UP/DOWN DECADE A N D BINARY COUNTERS M AR C H 1 9 8 4 - • • I Fully Synchronous Operation for Counting and Programming

74AS871

Contextual Info: TEXAS INSTR LOGIC NOTICE SEE ORDER OF DATA FOR ERRATA ESE D • fiU17S3 QOflBTEE 1 ■ T-Vg-0?-0? S N 5 4 A LS 8 70 , SN 5 4AS 8 70 , S N 5 4 A LS 8 71, SN 5 4 A S 8 71 S N 74 A LS 8 70 , S N 74 A S 8 70 , S N 7 4 A L S 8 7 1 , S N 74 A S 8 71 INFORMATION

54s373

Contextual Info: SN54LS373, SN 54 LS374, SN54S373, SN54S374, S N 74 LS 3 73 , S N 74 LS 3 74 , S N 74 S 3 7 3 , S N 74 S 3 7 4 OCTAL D-TYPE T R A N S P A R EN T LATCHES A N D EDGE-TRIGGERED FLIP FLOPS O C T O B E R 1 9 7 5 — R E V IS E D M A R C H 1 9 8 8 SN 54LS3 73. SN 5 4 LS3 7 4 , SN 54S37 3,

64LS138

Contextual Info: S N 5 4 LS 13 8 , SN 54S138, S N 74 LS 13 8 , S N 74 S 13 8 A 3-LINE TO 8-LINE D EC OD ERS/DEM U LTIPLEXERS DECEMBER 1972 —REVISED MARCH 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems I I 3 Enable Inputs to Simplify Cascading

SN74ALS176

Abstract: SN54ALS174 SN54ALS175 SN54AS174 SN54AS175A SN74ALS174 SN74ALS175 SN74AS174 SN74AS175A als174
Contextual Info: SN74ALS174, SN74ALS175, SN74AS174, SN74AS175A SN54ALS174, SN54ALS175, SN54AS174, SN54AS175A HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR D2661, APRIL 1 9 8 2 - REVISED M A Y 1986 S N 5 4A LS 1 74 , S N 5 4A S 1 74 . . . J PACKAGE S N 74A LS 174, S N 7 4 A S 1 7 4 . . . D OR N PACKAGE

LS1639

Abstract: 74ALS1639
Contextual Info: TYPES SN 54A LS1638, S N 54A LS1639, SN 74 A LS1 638 , S N 7 4 A LS 1 639 OCTAL BU S TRANSCEIVERS D2661, DECEMBER 1982-REVISED DECEMBER 1983 Bidirectional Bus Transceivers in High-Density 20-Pin Packages S N 54A LS 1638, S N 54A LS 1639 J PAC KA G E S N 74A LS 1638, S N 74ALS1639

Contextual Info: T Y P ES S N 5 4 ALS 242 A, SN 5 4ALS243 A, SN 54AS242, SN54AS243 S N 74 A LS 2 4 2 A , S N 74 A LS 2 4 3 A , S N 74 A S 2 4 2 , SN 74AS243 Q U AD R U PLE BUS TRAN SC EIVERS W ITH 3 S TA TE O U TPU TS D 2 6 6 1 , DECEMBER 1 9 8 2 -R E V IS E D DECEMBER 1 9 8 3

SRG8

Abstract: 74als165
Contextual Info: TYP ES S N 5 4 A LS 16 S , S N 74 A LS 16 5 P A R A LLE L LO AD 8-BIT SH IFT REGISTERS D 2 6 6 1 , JU N E 1982 Complementary Outputs I• • SN 54A LS 165 . . . J PACKAGE S N 74A LS 165 . . . N PACKAGE Direct Overriding Load Data Inputs (TOP VIEW) Gated Clock Inputs

54AS832

Abstract: 74As832
Contextual Info: PRODUCT PREVIEW SN 54A LS 832A , SIU54AS832B, S N 74 A LS 8 32A , S N 74 A S832 B HEX 2-INPUT OR DRIVERS D 2 6 6 1 , OEC EM B ER 1982 - R E V ISE D M A Y 1986 High Capacitive Drive Capability S N 5 4 A L S 8 3 2 A , S N 5 4 A S 8 3 2 B . . . J P AC KA G E

LS1623

Contextual Info: T Y P E S SN 54ALS1620 THRU SN54ALS1623 S N 74 A LS 16 2 0 THRU S N 74 A LS 16 2 3 OC TAL BUS TRAN SC EIVERS D 2 6 6 1 , D EC EM BER 1 9 8 2 - R E V IS E D D EC EM B ER 19B3 Bus Transceivers in High-Density 20-Pin DIPs and the New Plastic and Ceramic Chip Carriers Packages

MA161

Contextual Info: DN74LS54 LS T T L DN74LS Series DN74LS54 74 LS ^ 4 - wide AND-OR-INVERT Gates • Description DN74LS54 contains four 2-input and four 3-input AND-ORINVERT gates. ^0^ ■ Features • • • • Low power consumption Pa = 4.5mW typical High speed ( tpa = 12ns)

74s196

Abstract: 74196 TTL SN74S197 74S196 TTL
Contextual Info: SN54196, S N 5 4 19 7 , SN54LS196, S N 5 4 LS 19 7, SN54S196. S N 5 4 S 19 7, S N 74 1 9 6 , S N 7 4 1 9 7 , S N 74 LS 1 9 6 , S N 7 4 L S 1 9 7 , S N 74 S 1 9 6 , S N 7 4 S 1 9 7 50/30/1 OO MHz P R E S E T T A B LE DECADE OR BINARY COUNTERS/LATCHES OCTOBER 1 9 7 6 —REVISED M AR C H 1988

74as373

Abstract: LS 373
Contextual Info: T Y P ES S N 5 4A LS 3 73 , SN 5 4AS 3 73 , S N 74 A LS 3 73 . S N 74 A S 3 73 OC TAL D T Y P E TR A N S P A R EN T LA TC H ES W ITH 3-STATE OUTPUTS D2661, APRIL 1 98 2 -REVISED DECEMBER 1983 S N 54A LS373, S N 54A S 373 . . . J PACKAGE 8 Latches in a Single Package

N74s174

Contextual Info: S N 5 4 1 74 , S N 5 4 1 75 , S N 5 4 L S 17 4 , S N 5 4 L S 17 5 , S N 5 4 S 1 7 4 , S N 5 4 S 175 , SN 74 174 , SN 74 175 , SN 74 LS 174, SN 74LS175, S N 74 S 174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP FLOPS WITH CLEAR D E C E M B E R 1 9 7 2 - R E V l S E D M A R C H 1 9 8 8

Contextual Info: SN 5 4170 , S N 5 4 LS 170 , S N 74 170 , S N 74 LS 170 4 BY 4 REGISTER FILES WITH OPEN-COLLECTOR O U TPU TS M AR C H 1 9 7 4 - S e p a rate R e a d /W r ite A ddressing P erm its REVISED M AR C H 1 9 8 8 S N 5 4 1 7 0 , S N 5 4 L S 1 7 0 . . . J OR W PACKAG E

ALS6311

Abstract: sn74als6311 6311m
Contextual Info: S N 74 A L S 6 3 10 , S N 74 A LS 6 3 11 S TATIC C O LU M N A N D PA G E-M O D E AC C ES S D ETEC TO R S TO P V IE W C LK C 1 U C LK E N C 2 High-Performance Compare: 'ALS6310 CLK to HSA - 18 ns

SN54ALS620A

Abstract: SN74ALS620A SN74ALS623A SN74AS623 sn74als622
Contextual Info: SN54ALS620A THRU SN54ALS623A, SN54AS620 THRU SN54AS623 SN74ALS620A THRU SN74ALS623A, SN74AS620 THRU SN74AS623 OCTAL BUS TRANSCEIVERS D 2 6 6 1 , D E C E M B E R 1 9 8 2 - R E V IS E D M A Y 1 9 8 6 SN 54A LS', SN 54 A S' . . . J PACKAGE SN 74A LS', SN 74 A S' . . . DW OR N PACKAGE

74ALS01

Contextual Info: T YP ES S N 5 4 A LS 0 1, S N 74 A LS 0 1 QU AD RUPLE 2-INPUT POSITIVE-NAND G A TES WITH OPEN C OLLECTOR OUTPUTS D 2 6 6 1 . APRIL 1 9 8 2 -R E V IS E D DECEMBER 1 9 8 3 Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic

DN74LS373

Contextual Info: LS TTL DN74LS Series DN 74LS373 DN74LS373 K>74 LS. 373 Octal D-type Transparent Latches with 3 -sta te Outputs • Description D N 74L S 373 con tain s eight 3-state o u tp u t D -type latch circuits w ith com m on o u tp u t-c o n tro l enable in puts for all circuits.

74AS573

Abstract: ls58 SN54ALS573B sn74als573b
Contextual Info: S N54ALS573B, SN54ALS580A, SN54AS573, SN54AS580 S N 74 A LS 5 7 3 B , S N 74ALSS80 A, S N 74 A S 5 7 3 , SN74AS580 O C TAL D-TYPE T R A N S P A R EN T LATC HES WITH 3-STATE OUTPUTS D 2 6 6 1 , DEC EM BE R 1 9 8 2 - 3-State Buffer-Type Outputs Drive Bus-Lines

Contextual Info: 74 LS 2 5 8 A , S258 Sjgnelics Data Selectors/Multiplexers Quad 2-Line To 1-Line Data Selector/Multiplexer 3-State Product Specification Logic Products FEATURES • • • • Multifunction capability Inverting data path 3-State outputs See '257 for non-inverting

ls139

Contextual Info: SN74ALS139, SN54ALS139 DUAL 2-UNE TO 4-LINE DECODERS/DEMULTIPLEXERS 0 2 1 8 1 , A P R I L 1 98 2 - R E V I S E D M A Y 198 6 • • • • 8 N S 4 A LS 1 39 . . . . J P A C K A G E S N 74 A LS 1 39 . . . . D OR N PACKAGE Designed Specifically for High-Spaed

LS 273

Abstract: ls273
Contextual Info: T Y P ES S N 5 4 A LS 2 73 , S N 74 A LS 2 73 OC TAL D-TYPE FLIP FLO P S W ITH CLEAR D2661, APRIL 1982-REVISED DECEMBER 1983 • Contains Eight Flip-Flops w ith Single-Rail Outputs SN 54A LS273 . . . J PACKAGE SN 74A LS273 . . . N PACKAGE ITO P V IE W • Buffered Clock and Direct Clear Inputs

Contextual Info: GD54/74HC688, GD54/74HCT688 MAGNITUDE COMPARATOR/EQUALITY DETECTOR General Description These devices are identical in pinout to the 54 /74 LS 6 88. This circuit compares two 8-bit binary of BCD words and indicates whether or not they are equal. The comparator output indicates equality