644MHZ Search Results

AGILENT 1134A

Abstract: CF5037 r100ohm 54855A
Contextual Info: Nippon Precision Circuits Inc. Reference data : The output waveform of CF5037 200ps Waveform Differential 5ps Clock jitter - Measurement conditions Power supply voltage : 2.5V Output frequency : 644MHz(SAW) Differential Output Voltage (R=100ohm across OUT and OUTN)

10GHz OSCILLATOR pulse generator

Abstract: max3951 crystal 10Ghz MAX3930 MAX3952 10GHz serializer 10GHz laser oscillator MAX3952EGK prbs pattern generator
Contextual Info: 19-2405; Rev 0; 4/02 10Gbps 16:1 Serializer Features The MAX3952 16:1 serializer is optimized for 10.3Gbps and 9.95Gbps Ethernet applications. A serial clock output is provided for retiming the data at the latch input of the laser driver. Both the high-speed data and clock are

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC August 2004 Data Sheet Introduction The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORLI10G consists

CLK180

Abstract: MULT18X18 XAPP622 XC2V3000-FF1152 XC2V3000FF1152 sdr receiver
Contextual Info: Application Note: Virtex-II Series R 644-MHz SDR LVDS Transmitter/Receiver Author: Ed McGettigan XAPP622 v1.2 July 2, 2002 Summary This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one

p802

Abstract: 10GBASE-LR GR-468-CORE GR-63-CORE MF-11KMXE-001WA RIN12OMA te901
Contextual Info: MITSUBISHI CONFIDENTIAL TE9-01-253 Preliminary Data Sheet Approved 1 / 23 Nov. 2001. Charged MITSUBISHI OPTICAL DEVICES MF-11KMXE-001WA Signature by Customer Ethernet (LAN) Transceiver Module with MUX/DEMUX Ethernet 10GBASE-LR Transponder (with optional Heatsink)

Contextual Info: 100G Development Kit, Stratix V GX Edition User Guide 100G Development Kit, Stratix V GX Edition User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01111-1.1 Feedback Subscribe 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

four way traffic light controller vhdl coding

Abstract: vhdl code Wallace tree multiplier block diagram baugh-wooley multiplier vhdl code for Wallace tree multiplier vhdl code for traffic light control 8051 project on traffic light controller COOLRUNNER-II ucf file tq144 baugh-wooley multiplier verilog vhdl code manchester encoder traffic light controller vhdl coding
Contextual Info: Programmable Logic Design Quick Start Handbook R R Xilinx is disclosing this Document and Intellectual Property hereinafter “the Design” to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,

1-256 demultiplexer

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC November 2003 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

pin function of ic an 5522

Abstract: ltc5534 AN 5522 GRP1555C1H101J LT5522EUF GRP155R71C103K LMK316BJ475ML LT5522 LTC1748 ssb demodulator ic
Contextual Info: LT5522 400MHz to 2.7GHz High Signal Level Downconverting Mixer U FEATURES DESCRIPTIO • The LT 5522 active downconverting mixer is optimized for high linearity downconverter applications including cable and wireless infrastructure. The IC includes a high speed

ORLI10G

Abstract: ORLI10G-2BM680 STM-64 167MHZ isp connector block diagram
Contextual Info: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORLI10G Evaluation Board Measure the Performance of a 10Gbits/s Integrated Data Communication Solution Making the Right Choice… Programming and JTAG Download your design to the ORLI10G. Or, use board-specific evaluation bit streams.

644-Mhz

Abstract: AGILENT 1134A CF5037
Contextual Info: 日本プレシジョン・サーキッツ株式会社 東京都江東区福住ニ丁目 4 番3 号 参考資料：CF5037 series を使用した水晶発振器の出力波形 Waveform （Differential） 200ps ５ps Clock jitter ◆測定条件 ・ 電 源 電 圧 ：2 . 5 V

vhdl code for DES algorithm

Abstract: XAPP921c FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model verilog code for lms adaptive equalizer for audio LMS simulink 3SD1800A XILINX vhdl code REED SOLOMON encoder decoder fir filter with lms algorithm in vhdl code
Contextual Info: XtremeDSP Solutions Selection Guide June 2008 Introduction Contents DSP System Solutions.4 DSP Devices.17 Development Tools.25 Complementary Solutions.33 Resources.35

EZ 644

Abstract: 300-pin opnext OpNext 10gbase sr opnext l I64.1/10GBASE 2p 2.54 A0304 I-64.1 trv501 GR-253-CORE
Contextual Info: Technical Data Rev. 0.2, Sep. 5, 2005 TRV5026EZ-xx-x 10Gbit/s Transceiver with MUX/DMUX All specifications described herein are subject to change without prior notice TRV5026EZ-xx-x: 1310 nm OC192 for 7km / 2km application (SONET SR-1[1]/ SDH I64.1[2]) & 10GbE for 10km application (10GBASE-L[3]) Dual Protocol Transceiver

l28c

Abstract: MPC8260 ORLI10G STM-16 BM68
Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC January 2004 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

pir 644

Abstract: MAC layer sequence number
Contextual Info: PRELIMINARY CONFIDENTIAL CY7C9548 10-Gigabit Ethernet LAN PHY-POSIC10GLAN Features • Compliant with 802.3ae specifications[1] — Full-duplex media-access controller MAC data transmission and reception — 64B/66B PCS — Rate adaptation — Contains RMON for link statistics

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC February 2003 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

pin function of ic an 5522

Abstract: AN 5522 ssb demodulator ic 5522 lt GRP1555C1H101J GRP155R71C103K LMK316BJ475ML LT5522 LT5522EUF LTC1748
Contextual Info: LT5522 600MHz to 2.7GHz High Signal Level Downconverting Mixer U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT 5522 active downconverting mixer is optimized for high linearity downconverter applications including cable and wireless infrastructure. The IC includes a high speed

verilog code for 2-d discrete wavelet transform

Abstract: XAPP921c simulink universal MOTOR in matlab turbo encoder model simulink matched filter simulink simulink model for kalman filter using vhdl umts simulink fpga based wireless jamming networks dvb-rcs chip XAPP569
Contextual Info: XtremeDSP Solutions Selection Guide March 2008 INTRODUCTION Contents DSP System Solutions.4 DSP Devices.17 Development Tools.25 Complementary Solutions.33 Resources.35

smb 34

Abstract: SMB connector 0805HS-560TKBC MAX3953 MAX3953EVKIT MAX3953UGK SMP698
Contextual Info: 19-2607; Rev 0; 10/02 MAX3953 Evaluation Kit Features ♦ Single +3.3V Supply ♦ 9.953Gbps/10.312Gbps Evaluation ♦ Fully Assembled and Tested ♦ Fully Matched with High-Bandwidth SMP Connectors at the Input Component List DESIGNATION QTY Ordering Information

XC2V3000-FF1152

Abstract: XC2V3000FF1152 XAPP622 CLK180 MULT18X18 7SV11
Contextual Info: Application Note: Virtex-II Series R 644-MHz SDR LVDS Transmitter/Receiver XAPP622 v1.4 August 5, 2003 Summary This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one

Sanyo Denki encoder

Abstract: MPC8260 ORLI10G STM-16 L28a STM-16 chips 1-256 demultiplexer
Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC January 2005 Data Sheet Introduction The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORLI10G consists

L16A

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC April 2004 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

EEPROM 66B

Abstract: rx2b
Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC September 2002 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

VHDL code for lcd interfacing to spartan3e

Abstract: block diagram baugh-wooley multiplier vhdl code Wallace tree multiplier vhdl code for lcd of spartan3E VHDL code for lcd interfacing to cpld signetics hand book project report of 3 phase speed control motor circuit vector method philips application manchester verilog COOLRUNNER-II examples sd card interfacing spartan 3E FPGA
Contextual Info: Programmable [Guide Title] Logic Common UG Design Template Set Quick Start [Guide Subtitle] Guide [optional] UG500 v1.0 May 8, 2008 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development