60MBIT Search Results

LF4460

Contextual Info: LF4460 60-Mbit Video Memory / FIFO DEVICES INCORPORATED Product Brief FRAME MEMORY Features 60Mbit 62,092,800 bit memory density 150MHz Max clock rate Independent Read and Write ports: • Supports simultaneous read/write operations Selectable Memory Organization:

Contextual Info: LF4460 60-Mbit Video Memory / FIFO DEVICES INCORPORATED Preliminary Datasheet FRAME MEMORY Features 60Mbit 62,092,800 bit memory density 150MHz Max clock rate Separate independent Read and Write ports: • Supports concurrent read/write transactions Selectable Memory Organization:

hd-SDI driver

Abstract: HD-SDI LF44xx SDI SERIALIZER hd-SDI deserializer LF3312 LF3324 LF4460 HD-SDI camera parallel to HD-SDI
Contextual Info: DEVICES INCORPORATED Introducing - HD Frame Memory FRAME MEMORY Spend more time on product differentiation and less time juggling frames of video. Imagine a full-frame HDTV frame store solution in a single, tiny chip. Add a simple, easy to use SRAM interface and flexible addressing

L64705

Abstract: Viterbi decoder l64709
Contextual Info: L64705 FEC Concatenated Decoder Preliminary Specifications L64705.TAR.0 Draft 5/18/95 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications

DD54

Abstract: DD62 mrf 477 STI3500ACV DD15 DD47 DD48 DD49 DD50 PQFP144
Contextual Info: C 7 ^ 7 # . S C S -T H O M S O N « « L i O T STÌ3500A * ® MPEG-2 /C C IR 601 VIDEO DECODER • REAL-TIME DECODING OF MPEG-1 AND MPEG-2 VIDEO BITSTREAMS AT CCIR 601 RESOLUTION ■ FULLY SUPPORTS MPEG-2 MAIN PRO­ FILE/MAIN LEVEL MP@ML ■ VIDEO OUTPUT

receiver QAM schematic diagram

Abstract: ad646 AD922X "direct rf sampling" AD9042 satellite dish photo AD9220 AD9221 AD9223 82w40
Contextual Info: SECTION 5 HIGH SPEED ADC APPLICATIONS Walt Kester, Brad Brannon, Paul Hendricks DRIVING ADC INPUTS FOR LOW DISTORTION AND WIDE DYNAMIC RANGE In order to achieve wide dynamic range in high speed ADC applications, careful attention must be given to the analog interface. Many ADCs are designed so that

LF4460

Contextual Info: LF4415 15-Mbit Video Memory / FIFO DEVICES INCORPORATED Product Brief FRAME MEMORY Features 15Mbit 15,523,200 bit memory density 150MHz Max clock rate Independent Read and Write ports: • Supports simultaneous read/write operations Selectable Memory Organization:

STI5518

Abstract: transistor D331 circuit diagram application sti5518 jtag sti5505 sti5508 CCIR Report 624-4 STi5518 Register Manual LT 542 seven segment display data sheet STI5500 pin diagram of sti5518
Contextual Info: D I F N L A I T N E STi5518 SINGLE-CHIP SET-TOP BOX DECODER WITH MP3 AND HARD DISK DRIVE SUPPORT n n n n n n n n n n n n n Integrated 32-bit host CPU up to 81 MHz • 2 Kbytes of Icache, 2 Kbytes of Dcache, and 4 Kbytes of SRAM configurable as Dcache. Audio decoder

sti3520acv

Abstract: IDCT CCIR601 DD40 DD41 DD44 DD45 DD46 PQFP160 STI-350
Contextual Info: S G S -T H O M S O N " > !§ . B û D g œ [ L E Ê ir M D ( g § S T Í3 5 2 0 A MPEG AUDIO / MPEG-2 VIDEO INTEGRATED DECODER SUMMARY DATA • SINGLE CHIP IMPLEMENTING THE MPEG DECODING FUNCTIONS OF THE STi3500A VIDEO DECODER AND THE STi4500 AUDIO DECODER

hd-SDI deserializer

Abstract: HD-SDI LF44xx 27MHZ LF4460 hd-SDI reclocked
Contextual Info: HD-SDI Video Frame Synchronization DEVICES INCORPORATED LF44xx Video Memory Application Note FRAME MEMORY Overview Synchronization or Time Base Correction of an SDI video feed any format to arbitrary reference timing can be easily accomplished using the LF44xx. In this application, the LF44xx acts as a buffer or gasket between two independent

TCL COLOUR TV SCHEMATIC DIAGRAM

Abstract: xnxx BMS150 st1450 STI3500 STI3500 preliminary STI3520 4511 gm 71S1237 DD41
Contextual Info: "* J i, r Z 7 S G S - T H O M S O N M MSi sMM0(3i> STÌ3520 MPEG AUDIO / MPEG-2 VIDEO INTEGRATED DECODER PRELIMINARY DATA The STi3520 requires minimal support from an external microcontroller, which is mainly required to initialise the video decoder at the start of every

LF44xx

Abstract: LF4460 full hd video processor LF4415 "Frame rate conversion"
Contextual Info: LF4460 LF4430 LF4415 PRELIMINARY Video Memory / FIFO FRAME MEMORY Features Selectable I/O VDD = 1.8V, 2.5V, 3.3V Selectable Core VDD = 1.8V, 2.5V, 3.3V 172 ball FBGA package 15 x 15 x 1.4mm Depth expansion is supported for Multi-frame HDTV, Multiframe SDTV, and other formats:

Contextual Info: LF4430 30-Mbit Video Memory / FIFO DEVICES INCORPORATED Preliminary Datasheet FRAME MEMORY Features 30Mbit 31,046,400 bit memory density 150MHz Max clock rate Separate independent Read and Write ports: • Supports concurrent read/write transactions Selectable Memory Organization:

STI5500

Abstract: STi55 STi5500 st20 ST20 TOOLSET ST20C2 set top box block diagram LS 2027 Final Audio video rgb splitter amplifier schematic ST20 twin decoder A215
Contextual Info: STi5500 SET TOP BOX BACKEND DECODER WITH INTEGRATED HOST PROCESSOR PRELIMINARY DATA FEATURES • Enhanced 32-bit VL-RISC CPU - 50 MHz clock • fast integer/bit operation and very high code density ■ High performance memory/cache subsystem • 2 Kbytes Instruction cache, 2K bytes SRAM,

LSI L64002

Abstract: L64005 l64002 L64007 msb1310 L64768 LMC 447 SAR 444 L64007/
Contextual Info: Draft 1/16/97 Chapter 1 Introduction This chapter describes the system interface and features supported by the L64007 MPEG-2 transport demultiplexer. The chapter contains: ♦ Section 1.1, System Overview ♦ Section 1.2, Features 1.1 System Overview LSI Logic’s L64007 MPEG-2 DVB and JSAT compliant 32 PID transport

PLX9050

Abstract: PLX9080 Video Encoders SAA7112 QCIF samsung BT856 SAA7185 circuits AT2011 KS0125 KS0127
Contextual Info: A T 2 0 11 MPEG-1 Video CODEC
The AT2011 is a single chip video encoder / decoder optimized for real time compression and decompression based on the MPEG International Compression Standard. Specifications/Features z Supports I/P/B frame compression z Supports