5S33 Search Results

Contextual Info: 5S33 BiMOS n 32-BIT SERIAL-INPUT, LATCHED DRIVERS Designed to reduce logic supply current, chip size, and system cost, the UCN5833A/EP integrated circuits offer high-speed operation for thermal printers. These devices can also be used to drive multi­ plexed LED displays or incandescent lamps within their 125 mA peak

Contextual Info: —Advance Information— HD404508. HD4074509 D escription T he HD404508, H D 4 0 7 4 5 0 9 is a CMOS 4 -bit single-chip HMCS400 series m ic ro c o m p u te r p ro v id in g h ig h p ro g ra m p ro d u ctiv ity . It is s u ita b le for a d ig ital tu n in g sy ste m b y v irtu e

Contextual Info: l/ l co CONTACT CD NOT k SECTIONED. .j L j i 50 48 45 44 N 42 40 38 36 34 32 30 28 26 24 I O •. \ \ \ \ \ \ \ 22 20 18 16 14 w fm I SECT K C l A ~ S P A C E S X 2 ± 0 . 0 8 x - 12 10 x ~X~-'X tì = " B " ± 0 . 0 8 1.6*0.1 2 .6 J L. _ J1 O C~ REF * -

oec7

Contextual Info: DRAWI NG M A D E IN- T H I R D A N G L E P R O J E C T I O N A REVISIONS C o p y r i g h t 1 9 ~1 ¿ 5 b y A M P In c o rp o r a te d ,. H a r r is b u r g , P a . l l iNTTERNATiONAL R IG H J;S ' R E S E R V E D ^ AM P IN CO RPO RA TED PR O D U C T S

AC17-33

Contextual Info: P54/74FCT543T/AT/CT P54/74FCT544T/AT/CT OCTAL REGISTERED TRANSCEIVER jA- FEATURES • Function, Pinout and Drive Compatible with the FCT and F Logic ■ Power-off disable feature ■ Matched Rise and Fall times

Contextual Info: PRELIMINARY MICRON MT42C4256 883C AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • SMD 5962-89497, Class M • JAN 5962-89497, Class B • MIL-STD-883, Class B 28L/400 CDIP SC [ 1 SDQ1 [ 2 FEATURES • • • • • • • • • •

S4 59A

Abstract: S4 62a RB58 B9907 S4 5BA belden 9114 RB174 21-597
Contextual Info: pmV MS HADE IN THIRD AW3LE PROJECTION HIS DRAUIHÖ 13 UNPUBLISHED. I RELE ftEVtSICIWS AM RELEASE - 9 i PER 03 3 0 -0 2 3 6 -9 6 / l\ E 3V IE W V ] EW C A B LE USED W ITHO UT C A B LE U5ED W IT H 3. SEE B I .5 . 4. PARTS /5 \ U S E A SPA C ER SPA C ER 2790

XR-5532

Abstract: XR5532N XR-5532AN XR-5532P 5532N XR5532 XR5532P XR5532AN XR-5532AP XR-5532N
Contextual Info: JET EX4R X R-5532/5532A Dual Low-Noise Operational Amplifier GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM The XR-5532 dual low-noise operational amplifier is es­ pecially designed for applications in high quality profes­ sional audio equipment. The low-noise, wide bandwidth

ta 8742 IC

Abstract: 80836DX 80286 mouse 386R sl90 SL9030 SL9010
Contextual Info: y/a SL9095 Power M anagement Unit PRELIMINARY FEATURES • Supports 80286, 80386SX, 80386DX, and 80486 Page Mode or Cache-based Laptop designs. • IBM PC/AT Compatible. • Software Programmable Power Management Unit. Provides Individual On/Off Control. • Compatible with all CPU Clock Rates.

IDT7MP6104

Contextual Info: 128KB/256KB SECONDARY CACHE MODULE FOR THE INTEL i486 “ IDT7MP6104 IDT7MP6105 Integrated D evice T ech n olo g y, Inc. FEATURES DESCRIPTION • 128KB/256KB direct mapped, write-through, non-sectored, zero-wait-state secondary cache module • Ideal for use with ¡486-based systems

idt 256kb cache

Abstract: 7MP610
Contextual Info: bfiE D 1P x * 1dt Integrated Device Technology, Inc. • 4555771 D014S31 71S ■ IDT IDT7MP6104 128KB/256KB SECONDARY CACHE MODULE IDT7MP6105 FOR THE INTEL i486 INTEGRATED DEVICE FEATURES DESCRIPTION • 128KB/256KB direct mapped, write-through, non-sectored,

Contextual Info: SIEMENS C16x-Family of High-Performance CMOS 16-Bit Microcontrollers C167 Advance Information C167 16-Bit Microcontroller • • • • • • • • • • • • • • • • • • • • • • • • • • • • • High Performance 16-bit CPU with 4-Stage Pipeline

LT 01

Contextual Info: l/ l co CD CONTACT NOT k SECTIONED. .j L j i 50 48 45 44 N 42 40 38 36 34 32 30 28 26 24 I O •. \ \ \ \ \ \ \ 22 20 18 16 14 w fm I SECT K C l A ~ S P A C E S X 2 ± 0 . 0 8 x - 12 10 x ~X~-'X tì = " B " ± 0 . 0 8 1.6*0.1 2 .6 J L. _ J1 O C~ REF * -

VAM-03

Abstract: DDA010 VAM03 TL31 LA 4108 KDS 5.000 VAM02 ka bs 89 TL46 WO 8 94 00 KDS 8.000
Contextual Info: NEWBRIDGE MICROSYSTEMS SSE D • bSäfllOl 0 D G 0 7 3 1 3 ■ CA91C015 VMEbus DATA ADDRESS REGISTER FILE DARF T-52-33-S5 Complete VMEbus address and data Interface, exeept buffers Decoupling of CPU and VMEbus Sustained 25-30 Megabyte/second VMEbus transfer rate