5B2 3H Search Results

Contextual Info:

      

      
 
    

   
  
      
      
!"   #    


Contextual Info: BSO 305N I nf ineon technologies Preliminary Data SIPMOS Small-Signal-Transistor Product Summary Features 30 V • Dual N Channel Drain source voltage ^DS • Enhancement mode Drain-Source on-state resistance • Avalanche rated Continuous drain current

sk 8085

Abstract: hp5082 7651 74LS138 3 to 8 decoder notes 74LS138 decoder MP7651AS DDD7373 HP5082-2835 MC6800 MC68000 MP7651
Contextual Info: MP7651 8-Channel, Voltage Output 10 MHz Input Bandwidth 8-Bit Multiplying DACs with Serial Digital Data Port and Chip Select Decoder Z * E X A R FEATURES Low Harmonic Distortion: 0.25% typical with VREF = 1 V p-p @ 1 MHz Vr e f /2 Output Preset Level Latch-Up Proof

32-PIN

Abstract: DS2172 PS24 PS26 PS27 PS28 PS29 PS30 335 PR10
Contextual Info: DS2172 1 DALLAS s e m ic o n d u c t o r DS2172 Bit Error Rate Tester BERT PIN ASSIGNMENT FEATURES • Generates/Detects digital bit patterns for analyzing, evaluating and troubleshooting digital communica­ tions systems r • Operates at speeds from DC to 52 MHz

M1710a

Abstract: KHS04 NM2200 723 b14 smd diode BCY37 TD526 SA1218 20R5F BC23 7B 211 diode 6a6
Contextual Info: 8 &/. * 1 ,&6 3$*( &38 8 '0  6KHHW                                 & ' ',;21  &(/(521 6'5$0 &/. %8 ,&6 8  6+(7 ,1'(; 3$*( 3$*( '0 ',00  8 1%

CHN G4 141

Abstract: CHN G4 112 chn 711 chn 832 CHN 833 CHN G4 136 CHN G4 119 TS22 CHN G4 140 XRT86VL32IB
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JANUARY 2007 REV. 1.2.2 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

CHN G4 136

Abstract: CHN G4 319 CHN G4 117 CHN G4 CHN 922 equivalent CHN 703 SLC96 alarm frame format chn 711 chn 037 digital clock with alarm using 8051
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JULY 2006 REV. 1.2.0 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

CHN G4 136

Abstract: chn 711 CHN G4 141 CHN G4 124 CHN G4 137 CHN 423
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JANUARY 2007 REV. 1.2.2 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

chn 832

Abstract: CHN G4 112 H100 Block Diagram ST CHN 510 CHN 703 E1 PCM encoder XRT86VL34 chn 037 digital clock with alarm using 8051 ta 8268
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION OCTOBER 2007 REV. 1.2.3 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

DA05 display

Abstract: display DA05 U107D PIR CONTROLLER LP 0001 code 9397 750 00192 QFP100 SAB9077H SHRP001 mhrp02 cn/A/U 237 BG
Contextual Info: Philips Semiconductors Preliminary specification Picture-ln-Picture PIP controller SAB9077H FEATURES fi Display • 50/60 Hz PIP modes possible • Twin PIP in interlaced mode at 8-bit resolution • Sub-title mode features built in • Large display fine positioning area, both channels

CHN G4 136

Abstract: CHN G4 117 CHN G4 112 CHN G4 140 wireless 4-bit data transmission using 8051 64126 CHN 523 CHN G4 115
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JULY 2006 REV. 1.2.1 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

5b13

Abstract: IC LM 384 gn Ba 3d11
Contextual Info: FINAL COM ’L:-7/1 0 /1 2 /1 5 IN D :-1 0/1 2 /1 5 /2 0 M ACH5-384 M ACH5LV-384 V A A N N A M D T I S C O M P A N Y MACH5-3 84/120-7/10/12/15 MACH5-3 84/192-7/10/12/15 MACH5 -3 84/16 0-7/10/12/15 MACH5LV-384/120-7/10/12/15 MACH5LV-3 84/184-7/10/12/15 MACH5LV-384/192-7/10/12/15

ubee max

Abstract: NJU6577 NJU6577S NJUB577 SEG22 KJG V2 PS3760
Contextual Info: NJU6577 5 3 4 * ^ • m h t f y 7 8 O ' f e ? * i / ^ L C D > h t t i * K J7 " I ' / * s ■ N JU 6577I*. W 4, 240t* r i W 7 7 r ; * g 5 F : j W i£ t '»h W L C D K W h w T?, -»RAH. C P lM > » - 7 i« B I# . M >/M * M ' V W ^T? 8t*';h-/\, 7l/il', £ f d i W 7 J M > K 7 i « l w T , C P U f r e > &

47-bit

Abstract: S3ML-6888A uPD77220 GG33 upd77p220 JUPD77220
Contextual Info: N E C ELECTRONICS INC blE ]> • ^27525 JUPD77220, 77P220 ’•■vv,., 24-Bit Fixed-Point Digital Signal Processor NEC Electronics Inc. Description The /yPD77220 is a highly accurate digital signal pro­ cessor DSP . The pPD77220 has a mask ROM; the /JPD77P220 has a one-time program mable (OTP) or an

bc829

Abstract: scda samsung rv410 quanta u36 max8774 gst5009 lf samsung GDDR MAX8774 foxconn RSMRST quanta
Contextual Info: 1 2 3 4 5 6 7 ZC3 BLOCK DIAGRAM AMD K8/RX485/SB460 REV:B DDR II-SODIMM1 AMD S1 Turion 64 CPU THERMAL SENSOR Page 13 Page 7,8 Page 2 2X PCI-E 0,1 Page 32 Page 29 B ATI M56-P PCIE 16X NORTH BRIDGE RX485 1X PCI-E 3 CPU CORE MAX8774 Page 41 A +1.2V/+1.5V/+2.5V

Contextual Info: Preliminary Data Sheet August 1996 m icroelectronics Lucent Technologies Bell Labs Innovations group o LUC3X01 100Base-T4 Physical Layer Device Features and Benefits Description • VLSI CMOS Physical Layer Device supports the IEEE' 802.3u, 100Base-T4 CSMA/CD specifica­

CHN 648

Abstract: chn 542 CHN 612 diode CHN 552 CHN 628 CHN 522 CHN 632 chn 637 chn 621 CHN 631
Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.5 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

CHN 612 diode

Abstract: CHN 545 CHN 648 chn 542 CHN 519 ST chn 624 CHN 507 SCR PIN CONFIGURATION CHN 035 CHN 522 CHN 535
Contextual Info: áç XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO AUGUST 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

chn 924

Abstract: chn 648 equivalent
Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.3 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

chn 924

Abstract: CHN 643 144T1 CHN G4 120 chn 648 equivalent 1/CHN 545
Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO MAY 2004 REV. P1.1.1 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

CHN G4 141

Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO APRIL 2004 REV. P1.1.0 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

EPF8282

Contextual Info: FLE X 8000 Includes FLEX 8000A • OUUU Programmable Logic Device Family March 1995, ver. 6 Features. Data Sheet ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device family 2,500 to 16,000 usable gates

CHN G4 309

Abstract: 40 serice free DMO 565 R CHN 932
Contextual Info: xr XRT86L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JANUARY 2005 REV. P1.1.7 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

Contextual Info: AMDZI FINAL I i L r l r l Am486 DE2 8-Kbyte Write-Through Embedded Microprocessor DISTINCTIVE CHARACTERISTICS • High-Performance Design ■ ■ ■ Complete 32-Bit Architecture — 66-MHz operating frequency — Address and data buses — Frequent instructions execute in one clock