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THC63LVDM83A

Abstract: THC63LVD813 30 lvds LVDS 18bit THine THC63LVD823 THC63LVD823 application notes TD227 lvds 6bit thine electronic
Contextual Info: Preliminary THC63LVD813 Rev.0.62 THine THC63LVD813 Dual 170MHz Link LVDS Transmitter for SXGA/SXGA+/UXGA General Description Features The THC63LVD813 transmitter is designed to support Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions.

LVDS Transmitter THine

Abstract: THC63LVD823 tft lvds HSYNC, VSYNC, DE, input, output Diode B2x THC63LVDM83R 15 TFT 20 pin lvds dual pixel lvds 1 channel 6bit lvds driver thine electronic
Contextual Info: THC63LVD823_Rev2.0 THC63LVD823 Single 135MHz /Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA General Description Features The THC63LVD823 transmitter is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to

DS90C387R

Contextual Info: November 2000 DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA General Description The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution. It is designed to be compatible with Graphics Memory Controller Hub GMCH by implementing two

MAX9213ETM

Contextual Info: 19-2828; Rev 1; 7/03 Programmable DC-Balanced 21-Bit Serializers Features ♦ Programmable DC-Balanced or Non-DC-Balanced Operation ♦ DC Balance Allows AC-Coupling for Ground-Shift Tolerance ♦ As Low as 8MHz Operation Two frequency ranges and two DC-balance default

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

DS90CR216A

Abstract: DS90CR218A MAX9210 MAX9215 MAX9222
Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

MAX9220EUM

Contextual Info: 19-2864; Rev 1; 10/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215

Diode B2x

Abstract: THC63LVD824 THC63LVDF84B thine electronic
Contextual Info: THC63LVD824 _Rev2.0 THC63LVD824 Single 135MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824 receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to

FIN1216

Abstract: FIN1215 FIN1215MTDX FIN1216MTDX FIN1217 FIN1217MTDX FIN1218 FIN1218MTDX
Contextual Info: FIN1215 / FIN1216 / FIN1217/ FIN1218 LVDS 21-Bit Serializers / De-Serializers Features Description ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL Low-Voltage TTL data into three serial LVDS (Low-Voltage Differential Signaling) data

Contextual Info: THC63LVD1027_Rev.2.0_E THC63LVD1027 85MHz 10Bits Dual LVDS Repeater General Description Features The THC63LVD1027 LVDS Low Voltage Differential Signaling repeater is designed to support pixel data transmission between Host and Flat Panel Display up to WUXGA resolution.

Contextual Info: FIN3385 / FIN3386 Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer Features Description • •        The FIN3385 and FIN3386 transform 28-bit wide parallel Low-Voltage TTL LVTTL data into four serial Low Voltage Differential Signaling (LVDS) data streams. A

UTP cat 6 cable

Contextual Info: 19-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

FIN3385

Abstract: FIN3383 FIN3383MTD FIN3384 FIN3384MTD FIN3385MTD FIN3386 FIN3386MTD MTD56
Contextual Info: Revised April 2005 FIN3385 • FIN3383 • FIN3384 • FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers General Description Features The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL Low Voltage TTL data into 4 serial LVDS (Low

THC63LVDF84A

Abstract: THC63LVD824 THC63LVD814 thine electronic
Contextual Info: THine THC63LVD824 Rev.1.03 THC63LVD824 Single 135MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824 receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to

288a

Abstract: DS90CR217 DS90CR218A DS90CR218AMTD MTD48 LINK12 AN-1041 AN1041
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

Contextual Info: 19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing

Contextual Info: FIN1215 / FIN1216 / FIN1217/ FIN1218 LVDS 21-Bit Serializers / De-Serializers Features Description ̇ ̇ ̇ ̇ ̇ ̇ ̇ ̇ ̇ ̇ The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL Low-Voltage TTL data into three serial LVDS (Low-Voltage Differential Signaling) data

Contextual Info: THC63LVD1027_Rev.2.0_E THC63LVD1027 85MHz 10Bits Dual LVDS Repeater General Description Features The THC63LVD1027 LVDS Low Voltage Differential Signaling repeater is designed to support pixel data transmission between Host and Flat Panel Display up to WUXGA resolution.

FIN3385MTDX

Abstract: FIN3386MTDX 3385 FIN3383 FIN3383MTDX FIN3384 FIN3384MTDX FIN3385 FIN3386
Contextual Info: FIN3385 / FIN3383 / FIN3384 / FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Features Description ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ The FIN3385 and FIN3383 transform 28-bit wide parallel LVTTL Low-Voltage TTL data into four serial LVDS (Low Voltage Differential Signaling) data streams.

Contextual Info: DS90C387R www.ti.com SNLS062E – MAY 2004 – REVISED MAY 2004 DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA Check for Samples: DS90C387R FEATURES DESCRIPTION • The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9209GUM MAX9213 marking code 56l MAX9213ETM
Contextual Info: 19-2828; Rev 4; 10/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

MTD48

Abstract: transmission line theory 288a DS90CR217 DS90CR218A DS90CR218AMTD an-806 Link12 AN1108
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

THC63LVD824A

Abstract: 824A 16 PIN TTL parallel to vga THC63LVD824 THC63LVDF84B
Contextual Info: THC63LVD824A _Rev1.10_E THC63LVD824A Single 112MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to

THC63LVD824A

Abstract: THC63LVD824 THC63LVDF84B HSYNC, VSYNC, DE, input, output
Contextual Info: THC63LVD824A _Rev1.00_E THC63LVD824A Single 112MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to