54HCT00 Search Results

Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Changes are in accordance with the notice of revision 5962-R058-95. - tvn 95-01-31 Monica L. Poelking B Correct the title to accurately describe the device function. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial

IC 74LS00

Abstract: 74LS00 gate diagram nand IC TTL 74LS00 M74HCT00
Contextual Info: S G S -T H O M S O N jL iM s iO (g S M 5 4 H C T oo M74HCT00 QUAD 2-INPUT NAND GATE • H IG H S P E E D tp D = 12 ns (TYP.) AT V c c = 5 V ■ LO W PO W ER DISSIPATION Ice = 1 |iA (M AX.) A T T a = 2 5 °C ■ C O M P A TIB LE W ITH TTL O U TP U TS V ih = 2V (MIN.) V il = 0.8V (MAX)

SN54HCT00

Abstract: SN74HCT00
Contextual Info: 54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES S C LS 062A - NOVEMBER 1988 - REVISED JANUARY 1996 • Inputs Are TTL-Voltage Compatible • Package Options Include Plastic Small-Outline D , Thin Shrink Small-Outline (PW), and Ceramic Flat (W)

74hc00 fan-out

Abstract: 74HC00 harris 74HC00 74hc00 and gates 74HCT00M
Contextual Info: HARR IS S E M I C O N D SE C T O R 4302271 G0174SS 27E D CD54/74HC00 CD54/74HCT00 T File Number 1464 High-Speed CMOS Logic Quad 2-input NAND Gate Type Features: • 8 uttered inputs ■ Typical propagation delay = 7 ns @ V cc- 5V CL = 15 pF, Tfl = 25° C 9 2C S < 3 # 0Z flR I

74LS00 integrated circuit

Contextual Info: r z 7 S C S TH O M S O N Ä 7# 54HCT00 M74HCT00 QUAD 2-INPUT NAND GATE • HIGH SPEED tpD = 12 ns 7YP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 HA (MAX.) AT Ta = 25 ”C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX) ■ OUTPUTS DRIVE CAPABILITY

equivalent data book of 10N60 mosfet

Abstract: MC14016CP GD4511 an-6466 CX 2859 SMD 74AC14 spice 6120* harris HCF4018be 7028 SMD Transistor spice irfbc40
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