54LS7 Search Results

LS 7475

Abstract: C4408
Contextual Info: SN5475, SN5477, 54LS75, 54LS77. SN7475, SN74LS75 4 BIT BISTABLE LATCHES MAR CH 1 9 7 4 - each latch (TOP VIEW) OUTPUTS INPUTS REVISED M A R C H 1 9 8 8 SN 5475 , SN 54LS75 . . . J OR W PACKAGE S N 7475 . . . N PACKAGE SN 74LS 75 . . . D O R N PACKAGE

SN 5477

Contextual Info: TYPES SN5475, SN5477, SN54L75, SN54L77, 54LS75, 54LS77, SN7475, SN74LS75 4-BIT BISTABLE LATCHES M A R C H 1 9 7 4 - R E V IS E D D E C E M B E R 1 9 8 3 S N 5475, SN 54LS75 . . J OR W PACKAGE S N 54L75 . . . J PACKAGE S N 7475 . . . J OR N PACKAGE SN74LS75 . , . D, J OR N PACKAGE

Contextual Info: M M O T O R O L A M ilita ry 54LS 73A Dual J-K Flip-Flop W ith C lear ELECTRICALLY TESTED PER: MIL-M-38510/30101 M P O /////// The 54LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs

Contextual Info: g Military 54LS75 MOTOROLA 4-Bit Bistable Latch With Q and Q ELECTRICALLY TESTED PER: MIL-M-38510/31601 M The 54LS75 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. Information present at the data (D) input is transferred to

Contextual Info: M MOTOROLA M ilitary 5 4 LS 7 3 A Dual J-K Flip-Flop With Clear ELECTRICALLY TESTED PER: MIL-M-38510/30101 The 54LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that w hen the clock goes HIGH, the inputs are enabled and data will be accepted. The logic of the J and K inputs may

Contextual Info: M M ilita ry 5 4 L S 7 1 8 MOTOROLA P rogram m able Binary Counter MPO mini ELECTRICALLY TESTED PER: 54LS718 These monolithic devices are programmable, cascadable, moduloN-counters. The 54LS716 can be programmed to divide by any number (N) from 0 through 9, 54LS718 from 0 through 15.

MA3232

Abstract: MAX7845
Contextual Info: <8 > MOTOROLA M ilitary 54LS716 Programmable Decade Counter MPO ELECTRICALLY TESTED PER: 54LS716 These monolithic devices are programmable, cascadable, modulo-N-counters. The 54LS716 can be programmed to divide by any number N from 0 through 9, the 54LS718 from 0 through 15.

Contextual Info: M ilita ry 54L S 75 MOTOROLA. 4-B it B istable L atch W ith Q and Q MPO unm ELECTRICALLY TESTED PER: MIL-M-38510/31601 The 54LS75 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. Information present at the data D input is transferred to

Contextual Info: ^ M O T O R O L A M ilitary 5 4 LS7 4 A D u a l D -Type Flip-Flop W ith C le a r and P reset ELECTRICALLY TESTED PER: MIL-M-38510/30102 The 54LS74A dual e dg e -trig ge re d flip -flo p u tilizes S chottky TTL c irc u i­ try to produce high-speed D -type flip -flo p s . Each flip -flo p has in d iv id u a l

DM74LS74A

Contextual Info: 54LS74,54LS74A,DM74LS74A 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Literature Number: SNOS313A 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs

DM74LS74AN

Contextual Info: LS74A National ÉSA Semiconductor 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

Contextual Info: M M O T O R O L A M ilitary 54LS75 4 -B it B istable _ Latch W ith Q and Q ELECTRICALLY TESTED PER: MIL-M-38510/31601 M PO The 54LS75 is a 4-Bit D -Type Latch fo r use as te m p o ra ry sto ra g e fo r b in a ry in fo rm a tio n betw een processing lim its and in p u t/o u tp u t o r in d i­

54LS74

Contextual Info: LS74A National Semiconductor 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

m38510/06301

Abstract: M38510-06302 m38510 m38510/20702 M38510/00801 M38510/00104 m38510/01201 M38510/20802 82S62 M38510/01302
Contextual Info: JAN/SMD Devices JAN/SMD Source JAN/SMD Source JAN/SMD Source M38510/00101 5430 M38510/07701 54S138 M38510/31512 54LS163A M38510/00102 5420 M38510/07702 54S139 M38510/31601 54LS75 M38510/00103 5410 M38510/07801 54S181 M38510/31603 54LS259 M38510/00104 5400

Contextual Info: 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a

at 6462 ram

Contextual Info: MOTOROLA Military 54LS718 P ro g ram m ab le B in ary C o u n ter ELECTRICALLY TESTED PER: 54LS718 T h e se m o n o lith ic d evice s are p ro g ram m ab le , cascad ab le , moduloN -counters. T h e 5 4LS 71 6 can be p ro gram m ed to d ivid e by an y nu m b er

smd 6 pin als

Contextual Info: MOTOROLA Military 54LS716 P ro g ram m ab le D ecade C o u n ter ELECTRICALLY TESTED PER: 54LS716 These m o n o lith ic devices are p ro g ra m m a b le , cascadable, m o d u lo N -counters. The 54LS716 can be p ro g ra m m e d to d ivid e by a ny n u m b e r

Contextual Info: MOTOROLA Military 54LS76 A Dual J-K Flip-Flop With Clear and Preset ELECTRICALLY TESTED PER: MIL-M-38510/30110 The 54LS76A offers individual J , K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data w ill be accepted. The logic

MAX7845

Abstract: 54LS716
Contextual Info: M OTOROLA Military 54LS716 Programmable Decade Counter HPO lllllll ELE C TR IC A LLY TESTED PER: M PG 54LS716 These monolithic devices are programmable, cascadable, modulo-N-counters. The 54LS716 can be programmed to divide by any number N from 0 through 9, the 54LS718 from 0 through 15.

Contextual Info: 5477 54LS77 DESCRIPTION LOGIC SYMBOL FEATURES The “ 7 7 " is a Dual 2-Bit D -Latch offe re d in a 14-Pin fla t pack. Two Enable inputs are pro­ vided; each con trols tw o latches. When the Enable E is HIGH, inform ation present at a Data (D ) input is tra nsferred to th e Q o u t­

54ls75

Contextual Info: Signetics 54LS75 Latch Quad Bistable Latch Product Specification Military Logic Products FEATURES • 4-bit bistable latch ORDERING INFORMATION DESCRIPTION ORDER CODE DESCRIPTION 16-Pin Ceramic DIP 54LS75/BEA The 54LS75 has four bistable latches. Each 2-bit latch is controlled by an active

Contextual Info: & June 1989 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered D flip-flops with complementary outputs. The informa­

circuit diagram with IC 7476

Abstract: 74LS76A logic diagram of ic 7476 IC 7476 JK
Contextual Info: SN5476, 54LS76A, SN7476, SN74LS76A DUAL J K FLIP FLOPS WITH PRESET AND CLEAR DECEMBER 1 9 8 3 • Package Options Include Plastic and Ceramic OIPs and Ceramic Flat Packages • Dependable Texas Instruments Quality and Reliability SN 5476. SN 54LS76A . . . J PACKAGE

Contextual Info: M MOTOROLA Military 54LS76A Dual J-K Flip-Flop With Clear and Preset ELECTRICALLY TESTED PER: MIL-M-38510/30110 M The 54LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted.