52LEAD Search Results

USR24

Abstract: ssi protocol 73D2248
Contextual Info: SSI 73D2248/2348 & MNP5, V.42bis Datacom Modem Device Set i k m M s l m s ' A TDK Group/Company Advance Information January 1993 FEATURES DESCRIPTION The SSI 73D2248/2348 Chip Sets consists of two CMOS integrated circuits which provide the data pump and protocol functions required to implement a high

68HC708KL8

Abstract: CPU08 HC05 M146805 M6805 M68HC05 M68HC08 Nippon capacitors
Contextual Info: HC708KL8GRS/D REV. 1.0 68HC708KL8 General Release Specification July 14, 1997 CSIC Consumer and Smartcard Microcontroller Division Austin, Texas N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D General Release Specification Motorola reserves the right to make changes without further notice to

C4558

Abstract: C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447
Contextual Info: CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Features • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)

OR73

Abstract: 73k312l 73K222
Contextual Info: 0253^5 ÜDDTflTG MOb « S I L SSI 73K312L Bell 202,103 and CCITT V.23, V.21 Single-Chip Modem A TDK Group/Company Preliminary Data SILI CO N SYSTEMS INC DESCRIPTION L IE D December 1992 ~ 7S -3 Z -Ú > 5 FEATURES Bell 202, 103 and CCITT V.23, V.21 slngle-chlp

32F8020

Contextual Info: ju t 1 « * » SSI 32P4722 jilic o n á tík m í' Pulse Detector & Data Separator A TDK Group/Company Advance Information June 1993 DESCRIPTION FEATURES The SSI 32P4722 is a low power, high performance bipolar device that provides pulse detection, data synchronization, and ENDEC electronics on a single

idt7134

Abstract: CY7C1342 CY7C135
Contextual Info: fax id: 5203 ,.V.Ï.Ï.V.^ y nr' C Y 7C 135 Æ C Y p R E S S C Y 7C 1342 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features True Dual-Ported memory cells which allow sim ulta­ neous reads of the sam e memory location 4K x 8 organization

SPT5230

Abstract: SPT5230SCT 1022 load cell
Contextual Info: @ S P SPT5330 T 10-BIT, 36 MWPS TRIPLE VIDEO DAC SIGNAL PROCESSING TECHNOLOGIES APPLICATIONS FEATURES Desktop Video Processing CCIR-601 Video Signal Processing RGB Color Monitors Image Processing Direct Digital Synthesis 10-Bit Triple Video Digital-to-Analog Converter

upsd

Abstract: UPS3200 TQFP52 TQFP80 uPSD3200 uPSD3233B uPSD3233BV uPSD3234A uPSD3234A-40 uPSD3234BV
Contextual Info: uPSD3234A, uPSD3234BV uPSD3233B, uPSD3233BV Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY • The uPSD323X Devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD323X Devices of Flash PSDs feature dual banks of Flash memory, SRAM,

UT AT66

Contextual Info: DEVICE SPECIFICATION 20-OUTPUT CLOCK DRIVER FEATURES • 20 clock outputs: - Ten outputs at primary frequency, up to 80 MHz - Ten outputs at primary or 1/2 primary frequency, in two groups of five outputs • Leading edge skew for all outputs <0.5 ns • Proprietary output drivers with:

23TI

Abstract: UPS3200 TQFP52 TQFP80 uPSD3253B uPSD3253BV uPSD3254A uPSD3254BV uPSD325X BV-24
Contextual Info: uPSD3254A, uPSD3254BV uPSD3253B, uPSD3253BV Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY • The uPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM,

Contextual Info: DEVICE SPECIFICATION 20-O U TPU T LVTTL C LO C K DRIVER FEATURES • 20 clock outputs at primary frequency up to 100 MHz • All outputs are leading edge synchronized to within <0.5 ns • Proprietary output drivers with: - Complementary 24 mA peak outputs, source

8T33FS6221

Contextual Info: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout MC100ES6221 MC100ES6221 ECL/PECL/HSTL Clock Buffer PRODUCT DISCONTINUATION NOTICEFanout

W2L14Z225M

Abstract: LLA219C70G225M LTC5569 LTC2271 LTC5584 LTC5585
Contextual Info: LTC2271 16-Bit, 20Msps Serial Low Noise Dual ADC FEATURES DESCRIPTION n The LTC 2271 is a 2-channel, simultaneous sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that

G530T

Contextual Info: •HYUNDAI H Y 6 7 1 6 1 1 0 / 1 Ì 1 64K X 16 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a

cy7c131-55nc

Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex­

adsh 13

Abstract: intel 80486 CY7C1031 CY7C1032 VXXXX
Contextual Info: CY7C1031 CY7C1032 PRELIMINARY ?CYPRESS Functional Description continued Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) is LOW and (2) AD5P is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at Ao

ZE 004

Abstract: SPT5230 SPT5230SCT 1022 load cell ir3d
Contextual Info: SPTS230 @ S PT 10-BIT, 36 MWPS TRIPLE VIDEO DAC S/GNAL PROCESSING TECHNOLOGIES FEATURES APPLICATIONS Desktop Video Processing CCIFt-601 Video Signal Processing RGB Color Monitors Image Processing Direct Digital Synthesis 10-Bit Triple Video Digital-to-Analog Converter

atmel 80C52X2

Abstract: 80C52X2 AT89C5131A-RD at89c5131 parallel programmer AT89C5131 PLCC 52 AT89C5131 80C51 80C52 AT89C5131A-L PLCC52
Contextual Info: Features • 80C52X2 Core 6 Clocks per Instruction • • • • • • • • • • • • • • • • • • • – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters: T0, T1 and T2

1E76

Abstract: 00FF M68HC05 65r5 S002D non-user mode
Contextual Info: Order this document by MC68HC05M4TS/D REV. 1 MOTOROLA SEMICONDUCTOR m m TECHNICAL DATA MC68HC05M4 Technical Summary 8-Bit Microcontroller Unit The MC68HC05M4 HCMOS microcontroller unit MCU is a member of the M68HC05 Family of microcontrollers. This high-performance, low-power MCU has parallel I/O capability with pins programmable as input or output. Addi­

LVEP221

Abstract: NB100LVEP221 NB100LVEP221FA NB100LVEP221FAR2
Contextual Info: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential

AN1545

Abstract: MPC961C MPC991 analog vco
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 3.3V Differential ECL/PECL Order Number: MPC9991/D Rev 0, 12/2001 MPC9991 PLL Clock Generator The MPC9991 is a 3.3 V compatible, PLL based ECL/PECL clock driver. Using SiGe technology and a fully differential design ensures

AD1839A

Abstract: AD1839AAS AD1839AAS-REEL OP275 TDM256
Contextual Info: a 2 ADC, 8 DAC, 96 kHz, 24-Bit ⌺-⌬ Codecs AD1839A FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports up to 96 kHz Sample Rates 192 kHz Sample Rate Available on 1 DAC Supports 16-/20-/24-Bit Word Lengths Multibit ⌺-⌬ Modulators with

LVE222

Abstract: MC100LVE222 MC100LVE222FA MC100LVE222FAR2 MB113
Contextual Info: MC100LVE222 3.3 V ECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single- ended with VBB output reference bypassed and connected to the

Contextual Info: PRELIMINARY '# CYPRESS 32Kx 18 Synchronous Cache RAM Features • Direct interface with the processor and external cache controller • Supports 66-MHz Pentium micro­ processor cache systems with zero wait states • Asynchronous output enable • I/Os capable o f 3.3V operation