500PS Search Results

Contextual Info: QUINT LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ SY100E417 3.3V and 5V power supplies required Also, supports LVPECL-to-PECL translation 500ps propagation delays Fully differential design Differential line receiver capability

"dj cd"

Abstract: circuit mri oscillator
Contextual Info: * SYNERGY C o p yC lo ck m Clockworks " S E M IC O N D U C T O R FEATURES D E S C R IP T IO N Less than 500ps of edge skew between any two outputs — FOREVER Master, plus up to 3 slaves, provide up to 32 TTLcom patible outputs per board Clock frequencies to 125MHz

Contextual Info: SING LE SUPPLY Q U A D P EC L-TO -TTL Clockworks SY10H842 W /LA TC H E D O UTPUT E N A B L E sÈ llb ólÌD U C T O R SY100H842 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

Contextual Info: Standard Products UT200SpWPHY01 SpaceWire Physical Layer Transceiver Datasheet August, 2006 INTRODUCTION FEATURES ‰ 2-bit Serializer/Deserializer SerDes functionality ‰ LVDS physical layer ‰ Data rates to 200 Mbits/sec ‰ Data/Strobe transmit skew <500pS

Contextual Info: Standard Products UT200SpWPHY01 SpaceWire Physical Layer Transceiver Advanced Datasheet April 20, 2006 INTRODUCTION FEATURES ‰ 2-bit Serializer/Deserializer SerDes functionality ‰ LVDS physical layer ‰ Data rates to 200 Mbits/sec ‰ Data/Strobe transmit skew <500pS

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER FEATURES: 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps max. Very low duty cycle distortion < 600ps (max.) Low CMOS power levels TTL compatible inputs and outputs TTL level output voltage swings High drive: - 32mA Io h , +48mA Io l

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER FEATURES: 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps max. Very low duty cycle distortion < 600ps (max.) Low CMOS power levels TTL compatible inputs and outputs TTL level output voltage swings High drive: - 32mA Io h , +48mA Io l

Contextual Info: IDT49FCT805BT/CT IDT49FCT806BT/CT FAST CMOS BUFFER/CLOCK DRIVER Integrated Device Technology, Inc. FEATURES: Military product compliant to MIL-STD-883, Class B • » • • • • • • • • • 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps max.

smd a60

Abstract: LTC1518 LTC1688 LTC1689 ltc1688cs
Contextual Info: LTC1688/LTC1689 100Mbps RS485 Hot Swapable Quad Drivers U DESCRIPTIO FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Ultrahigh Speed: 100Mbps Guaranteed Propagation Delay: 8ns ±4ns Over Temperature 50Mbps Operation with VDD = 3V Low Channel-to-Channel Skew: 500ps Typ

SENSYM

Abstract: sensym pressure transducers SENSYM 19C SENSYM ict SENSYM* 19 Foxboro OR ICT SENSYM 19 u 100 sensym 1500 005PG SENSYM 150
Contextual Info: 19C Series 0 to 3psi to 0 to 500psi Low Cost, Stainless Steel Isolated Pressure Sensors Sensor Systems General Description The stainless steel 19C Series devices were developed for pressure applications that involve measurement of hostile media in harsh environments. These sensors will accommodate any media

Contextual Info: ClockWorks SY10H841L SY100H841L FINAL 3.3V SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE DESCRIPTION FEATURES • ■ ■ ■ ■ 3.3V power supply Translates positive ECL to TTL PECL-to-TTL 300ps pin-to-pin skew 500ps part-to-part skew Differential internal design for increased noise

Contextual Info: SY100ELT24 TTL-to-DIFFERENTIAL ECL TRANSLATOR SYNERGY SY100ELT24 SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ DESCRIPTION 500ps typical propagation delay Differential ECL output PNP TTL input for minimal loading Flow-through pinouts ESD protection of 2000V

Contextual Info: QUINT LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ SY100E417 FINAL 3.3V and 5V power supplies required Also, supports LVPECL-to-PECL translation 500ps propagation delays Fully differential design Differential line receiver capability

Contextual Info: SY10E101 SY100E101 FINAL QUAD 4-INPUT OR/NOR GATE FEATURES DESCRIPTION • ■ ■ ■ 500ps max. propagation delay Extended 100E VEE range of –4.2V to –5.5V True and complementary outputs Fully compatible with industry standard 10KH, 100K I/O levels ■ Internal 75KΩ input pulldown resistors

Contextual Info: „.x SYNERGY „ n SY100484-3.5/4 SY101484-3.5/4 SY100484-5/6 S Y101484-5/6 a iiji SEMICONDUCTOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ Address access time, tAA: 3.5/4/5/6ns max. Chip select access time, tAc: 3ns max. Edge rate, tr/tf: 500ps typ.

Contextual Info: * QUAD 4-INPUT OR/NOR GATE SYNERGY SY10E101 SY100E101 SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ 500ps max. propagation delay True and complementary outputs ESD protection of 2000V Fully compatible with industry standard 10KH, 100K I/O levels ■ Extended 100E V e e range of -4.2V to -5.46V

Contextual Info: SYNERG Y TRIPLE ECL/LVECL-TOPECL/LVPECL TRANSLATOR SY100EL90V SEMICONDUCTOR DESCRIPTION FEATURES 3.3V and/or 5V power supply options 500ps propagation delay Fully differential design Supports both standard and low voltage operation ESD protection of 2000V

Contextual Info: SINGLE SUPPLY QUAD PECL-TO-TTL OUTPUT ENABLE SYNERG Y Cl0c1i °r^ '" SY100H842 SEMICONDUCTOR DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

74FCT3805

Contextual Info:  FAST CMOS BUFFER/CLOCK DRIVER IDT54/74FCT3805/A ADVANCE INFORMATION Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • • • • 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps max. Very low duty cycle distortion < 1.0ns (max.)

ICS932S421B

Abstract: 1340G CK410B DOT96 ICS932S421 CK410B-generation
Contextual Info: DATASHEET PCIe Gen2 and QPI Clock for Intel-Based Servers ICS932S421B Key Specifications: • PCIe Gen 2 compliant SRC outputs • QPI & FBD 2 compliant CPU clocks • CPU cycle-cycle jitter: < 50ps • SRC cycle-cycle jitter: < 125ps • PCI cycle-cycle jitter: < 500ps

Contextual Info: f""* 1 3.3V D U A L D I F F E R E N T I A L S Y N ER G Y P E C L-to -n t L/ \ r j o Ku f' ^ m I ^ ; PQE, , 71i translator S E M IC O N D U C T O R " ' ' “ DESCRIPTION FEATURES • 2.0ns typical propagation delay ■ <500ps typical output-to-output skew ■ Differential PECL inputs

Contextual Info: * SYNERGY SEMICONDUCTOR QUAD 4-INPUT OR/NOR GATE FEATURES • 500ps max. propagation delay ■ Extended 100E V ee range of -4.2V to -5.5V ■ True and complementary outputs SY10E101 SY100E101 DESCRIPTION The SY10/100E101 are quad 4-input OR/NOR gates designed for use in new, high-performance ECL systems.

Contextual Info: V Clockworks PRELIMINARY 3.3V SINGLE SUPPLY QUAD PECL-TO-TTL OUTPUT ENABLE SYNERGY SEMICONDUCTOR o v iS i? !" SY100H842L DESCRIPTION FEATURES • 3.3V power supply ■ Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew

DL140

Abstract: MC100E101 MC10E101
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 4ĆInput OR/NOR Gate MC10E101 MC100E101 The MC10E/100E101 is a quad 4-input OR/NOR gate. • 500ps Max. Propagation Delay • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors QUAD 4-INPUT