500N Search Results

DAC1253X

Contextual Info: DAC1253X 0.25µ µm 2.5V 12-bit 2MSPS DAC GENERAL DESCRIPTION DAC1253X is a CMOS 12Bit D/A converter for general application. This digital to analog converter has a R-string structure. Its settling time is 500ns Typical value . FEATURES — Resolution: 12Bit

DAC1236X

Contextual Info: DAC1236X 0.25µ µm 1.8V/2.5V 10-BIT 2MSPS DAC GENERAL DESCRIPTION DAC1236X is a CMOS 10Bit D/A converter for general application. This digital to analog converter has a R-string structure. Its settling time is 500ns Typical value . FEATURES — Resolution: 10Bit

1SS321

Contextual Info: 1SS321 SILICON EPITAXIAL SCHOTTKY BARRIER TYPE LOW VOLTAGE HIGH SPEED SWITCHING. Low Forward Voltage Unit in mm VF=0.42V Typ. Low Reverse Current lR=500nA(Max.) Small Package SOT-23MOD MAXIMUM RATINGS (Ta=25°C) CHARACTERISTIC SYMBOL Maximum(Peak Reverse Voltage

SHC85

Abstract: MAS1001 ADSHC-85ET SAMPLE HOLD sample/track hold AD579 AD7501 AD7503 ADSHC-85 HAS-1002
Contextual Info: ANALO G D E V IC E S Fast 0.01% Track/Sample-and-Hold Amplifiers ADSHC-85 FEATURES Im proved SHC-85 Replacement 500ns Sam ple-to-H old Transient 5 0 |iV rms Noise Low Droop Rate o f 0.2m V/m s A D S H C -85 F U N C T IO N A L B L O C K D IA G R A M APPLICATIONS

AM9101

Abstract: P2101 am2101 AM9101CPC AM9101PC AM9101ADC AM9101BPC l01a #500 P2101-1 9101C
Contextual Info: Am9101/Am91L01/Am2101 FAMILY 256x4 Static R /W Random A cce ss Memories PART NUMBER Am2101 Am2101-2 Am 9l01 A Am91 L01A Am2101 -1 Am 9101B Am 91L01ß Am9101C Am91 L01C Am 9101D A CCESS TIME 1000ns 650ns 500ns 400ns 300ns 250ns D IS T IN C T IV E C H A R A C T E R I S T I C S

MSP430

Abstract: TPS780 TPS78223DDCR TPS78233 TSOT23-5 TPS78233DDCT
Contextual Info: TPS782xx www.ti.com SBVS115B – AUGUST 2008 – REVISED MAY 2010 500nA, IQ 150mA, Ultra-Low Quiescent Current Low-Dropout Linear Regulator FEATURES DESCRIPTION • • • • • • The TPS782 family of low-dropout regulators LDOs offers the benefits of ultra-low power (IQ = 1mA), and

2SA1681

Abstract: 2SC4409
Contextual Info: 2SC4409 TOSHIBA Transistor Silicon NPN Epitaxial Type PCT Process 2SC4409 Power Amplifier Applications Power switching applications Unit: mm • Low collector saturation voltage: VCE (sat) = 0.5V (max) (at IC = 1A) • High speed switching time: tstg = 500ns (typ.)

Contextual Info: ENGINEERED COMPONENTS CO 3ÛE D 33 3 32 A3 0 00 07 b 5 1 *EGC r-äi-n l&pprofilt t 2l COMFATIBLE DIP PULSE GENERATOR MODULE M íní # # # # # T 2 L input and output Pulse w idths stable and precise 8-pin DIP package Available in pulse w idths from 5 to 500ns

Contextual Info: lowproflit & -nv t 2l COMPATIBLE 1 £c 2 32*40 DIP LOGJC DELAY MODULE M ìn ì 2 l input and outputs Delays stable and precise 8-pin DIP package .250 high Available in delays from 25 to 500ns 20% taps — each isolated and with 10 Schottky T2|_ fan-out capacity

Contextual Info: lewprofile BP*11" 2 % 32 4 40 t 2l COMFATIBLE DIP LOGIC DELAY LINE T2|_ input and output Delay stable and precise 8-pin DIP package .250 high Available in delays from 5 to 500ns Output isolated and with 10 Schottky T 2L fan-out capacity Rise time 4ns maximum

Contextual Info: lawprofile NCED CMOS COMPATIBLE AWSTABLE C DELAY LINE # # # # T ^L com patible input and output Standby pow er 5 nano w a tts max. Delay stable and precise 16-pin DIP package .2 5 0 high # Available in delays from 15 to 500ns # O utput isolated and w ith 10 T ^L

Contextual Info: Im?profile t 2l COMPATIBLE LEADLESS CHIP CARRIER LOGIC DELAY MODULE t 2 l input and outputs Delays stable and precise Leadless Chip Carrier .240 high Available in delays from 25 to 500ns 20% taps — each isolated and with 10 Schottky T2|_ fan-out capacity

Contextual Info: lozv profite t 2l COMPATIBLE SIP LOGIC DELAY LINE M ini T 2 L FAST input and output Delay stable and precise 5-pin SIP package .350 high Available in delays from 5 to 500ns Output isolated and w ith 10 T 2L fan-out capacity Rise time 4ns m axim um design notes

AD509J

Abstract: AD509 AD509K 1N914 AD509S AD590K AD590
Contextual Info: ► High Speed, Fast Settling 1C Op Amp ANALOG DEVICES FEA TUR ES Fast Settling Time 100% Tested 0.1% in 500ns max 0.01% iin 2.5jus max High Slew Rate: I O O V / jlis min Low l os: 25nA max Guaranteed V os D rift: 30,uV/oC max HighCM FIR: 80dB min Drives 500pF

SIS 651

Abstract: MAX333 MAX333C MAX333M
Contextual Info: 1AX333 9 ^ -, SPDT C M O S 7 t n y - X'f f spDT # « « ! c M o s ig < o 7 + o ü ' •x-f S t S f F Ä i n l t g 'e * 4 . X -f K) v^x-.mwm, ? • t~-7 ■*■r • y -f jft* ? — V ^ V Ü iir a te i c f f i * ? — V + v a t l H I i - t n i « 500ns fo-«tCF 1000ns T

CA741CA

Abstract: CA1458E lm741 noise A0741 LM741N LM741 RCa741 lm 1458 high pass filter specification IC 741C ic lm741
Contextual Info: CA741, CA741C, CA1458, qA 7558, LM741, LM741C, LM1458 HARRIS s e m i c o n d u c t o r Single and Dual, High Gain Operational Amplifiers for Military, Industrial and Commercial Applications November 1996 Features Description • Input Bias C u rre n t. 500nA Max

p55g

Abstract: ST9293 ST9293J1 ST9293J3 ST9293J5 ST9293J7 on screen display
Contextual Info: ST9293  48K ROM HCMOS MCUs WITH ON SCREEN DISPLAY AND A/D CONVERTER FUNCTIONAL DESCRIPTION Register oriented 8/16 bit CORE with RUN, WFI and HALT modes Minimum instruction cycle time: 500ns 12MHz internal 16 to 48K bytes of ROM, 256 to 768 bytes of RAM,

TPS780180300

Abstract: Ldo regulator
Contextual Info: TPS780 Series www.ti.com . SBVS083C – JANUARY 2007 – REVISED MAY 2008 150mA, Low-Dropout Regulator, Ultralow-Power, IQ 500nA

Contextual Info: lowprofile ECL COMPATIBLE LOGIC NOISE FILTER MODULE # # # # # ECL in p u t and o u tp u t Pulse W idth Detection stable and precise 16-pin DIP package .250 high Available in pulse widths fro m 5ns to 500ns 70 ECL DC fan-out capacity T he E C L N F M is o ffe re d in 24 pulse w id th s fro m 5ns to 500ns,

ram 8108

Abstract: 8108-5CD EMM 8108
Contextual Info: SEMI 8108 300NSEC, STATIC, T TL IN /O U T1024 X 8 N-MOS RAM SEMI 8108 500NSEC, STATIC, TTL IN /O U T 1024 X 8 N-MOS RAM FE A T U R E S G E N E R A L D E S C R IP TIO N • 1024 w o rd s X 8 bits EM M S E M I'S 8 1 0 8 is a 8 1 9 2 -b it sta tic R A M , ■

Contextual Info: lawprofile t 2l COMFATIBLE LEADLESS CHIP CARRIER LOGIC DELAY MODULE T 2 L input and outputs The L C L D M -T T L is offered in 19 delays from 25ns to 500ns Delays stable and precise w ith each module incorporating taps at 20% increments of total Leadless C hip Carrier .2 4 0 high

SM DELAY LINES

Contextual Info: surface mount t 2l COMPATIBLE Wee DIP LOCIC DELAY LINE # T2L FAST in p u t and o u tp u t # Delays stable and precise # SO-14 pin pattern # Wee DIP package .235 high # A vailable in delays from 5 to 500ns The SM FLD L-TTL is offered in 76 delays from 5 to 500ns. Delay

Contextual Info: iozv profile t 2l COMPATIBLE DIP LOGIC DELAY LINE IVIìnì # T^L FAST input and output # Delay stable and precise # 8-pin DIP package # Leads—Thru-hole, J, Gull Wing or Tucked # Available in delays from 5 to 500ns # Output isolated and with 10 T2L fan-out

T2742

Abstract: riaa opa Burr-Brown IC appendix d
Contextual Info: OPA6O6 For Im séiate Assistants, Contact four Local Salesperson APPLICATIONS • WIDE BANDWIDTH: 13MHz typ • HIGH SLEW RATE: 35V/^s typ • • • • • LOW BIAS CURRENT: 10pA max at Ta = +25°C • LOW OFFSET VOLTAGE: 500nV max • LOW DISTORTION: 0.0035% typ at 10kHz