5000NS Search Results

PTTLDL-14-1

Abstract: ky 202 h PTTLDL-14-5 PTTLDL-14-2 PTTLDL-14-3 5000N LDL-14-1 PTTLDL14-5
Contextual Info: lowprofile t 2l COMPAT1BL 6-BIT DELAY LINE # # # T 2 l in p u t and o u tp u t Delays stable and precise 48 pin DIP package .250 high # # Available in delays up to 329ns Available in 5 delay steps w ith resolution fro m 1 to 5ns Propagation delays fu lly compensated

Contextual Info: lewprofile t 2l COMFATIBLE 6-BIT -I;:.! _ % # # # # # % # LOGIC DELAY LINE T2|_ input and output Delays stable and precise 48-pin DIP package .250 high Available in delays up to 329ns Available in 5 delay steps with resolution from 1 to 5ns Propagation delays fully compensated

Contextual Info: birprofile’ t 2l COMPATIBLE 8-BIT RAMMABLE DELAY LINE T 2 L input and output Delays stable and precise 64-pin D IP package .250 high Available in delays up to 1295ns Available in 5 delay steps with resolution from 1 to 5ns Propagation delays fu lly compensated

Contextual Info: tow profile t 2l COM PATIBLE 3-BIT AMMABLE LOGIC LAY LINE S ch ottky T 2 L c irc u its . These m odules are of hybrid con­ stru ctio n u tilizin g the proven te ch n o lo g ie s of active inte ­ grated c irc u itry and of passive netw orks u tilizin g capacitive,

Contextual Info: lowprofile t 2l COMFATIBLE 8-BIT PROGRAMMABLE LOGIC DELAY LINE T 2 l input and output Delays stable and precise 64-pin D IP package .250 high Available in delays up to 1295ns Available in 5 delay steps w ith resolution from 1 to 5ns Propagation delays fully compensated

Contextual Info: lowprôfile t 2l COMPATIBLE 6-BIT PROGRAMMABLE LOGIC DELAY LINE # # # # # # # # T2|_ input and output Delays stable and precise 48-pin DIP package .250 high Available in delays up to 329ns Available in 5 delay steps with resolution from 1 to 5ns Propagation delays fully compensated

Contextual Info: lowprofile t 2l COMPATIBL 8-BIT DELAY LINE are o f h y b rid c o n s tru c tio n u tiliz in g th e pro ven tech nolog ies o f # T 2 l input and output # Delays stable and precise # 64-pin DIP package .2 50 high % Available in delays up to 1295ns a high M T B F .

Contextual Info: lowprofile t 2l COMPATIBLE 3-BIT LEADLESS CHIP CARRIER PROGRAMMABLE LOGIC DELAY LINE in a minimum-sized leadless chip carrier package com patible w ith T^L input and output Schottky T ^L and DTL circuits. These modules are of hybrid con­ Delays stable and precise

Contextual Info: [oiv profile t 2l CO M PATIBLE 3-BIT AMMABLE LOGIC AY UNE T2L input and output Delays stable and precise 14-pin DIP package ""Si.V s?»J Leads - thru-hole, J, Gull Wing or Tucked # Available in delays up to 355ns # Available in 23 delay steps with resolution

delay line 400ns

Contextual Info: lowprofile ECL COMPATIBL 8-BIT PROGRAMMABLE LOGIC DELAY LINE ECL input and output levels Delays stable and precise 64-pin D IP package .2 5 0 high Available in delays up to 1287ns Available in 5 delay steps w ith resolution from 1ns to 5ns Propagation delays fu lly compensated

Contextual Info: lowprofile ECL COMPATIBLE 6-BIT PROGRAMMABLE LOGIC DELAY LINE # ECL input and output levels # Delays stable-and precise # 48-pin DIP package .2 5 0 high # Available in delays up to 323ns # Available in 5 delay steps with resolution from 1 to 5ns # Propagation delays fully compensated

Contextual Info: C2 Interface Silicon Labs Specification C2 Interface The Silicon Labs 2-Wire Interface C2 is a two-wire serial communication protocol designed to enable in-system programming, debugging, and boundary-scan testing on low pin-count Silicon Labs devices. C2 communication involves an interface master (the programmer/debugger/tester), and an interface

lcd cog spi 96x49

Abstract: STE2007 96x49 PAD85 COM19 LR019 lcd cog 51435
Contextual Info: STE2007 96 x 68 Single Chip LCD Controller/Driver Features • 68 x 96 bits Display Data RAM ■ 33,49, 65 and 68 Lines Mode ■ Row by Row Scrolling ■ Interfaces – 3-lines Serial Interface read and write – I2C (read and write) – 4-Line Serial (read and write)

ttl 217 202

Contextual Info: 4-Bit Programmable FAST TTL Logic Delay Line - EC2 1 of 5 Home EC2 . Robison Electronics Cornucopia Contact Us PROGRAMMABLE LOGIC DELAY LINES Background Passive Delay Lines Active Delay Lines

Contextual Info: lewprofile t 2l COMPATIBL 4-BIT PROGRAMMABLE LOGIC DELAY LINE # T2|_ input and output # Delays stable and precise # 32-pin D IP package .25 0 high cap acitive, in d u c tiv e and resistive elem ents. 9 Available in delays up to 765ns these m odules are bu rn e d -in to Level B o f M l L -S T D -8 8 3 to ensure

Contextual Info: PRODUCT: GPS/GNSS PATCH ANTENNA Part No. 1002428 Embedded GPS Ceramic Patch Antenna GPS/GNSS, 25x25x4 mm KEY BENEFITS Ethertronics’ series of GPS Ceramic Patch Antennas deliver on the key needs of device designers for higher functionality and performance in M2M designs.

Contextual Info: E N G I N E E R E D C O M P O N E N T S C bOE D 33335Ô3 n o a Q 7 tn 55Ô • EGC lozu profile t 2l CO M PATIBLE 4-BIT AMMABLE OCIC AY LINE # T2 L input and output # Delays stable and precise # 24-pin DIP package Leads - thru-hole, J, Gull Wing or Tucked

Delay Modules

Contextual Info: Home EC2 Robison Electronics Cornucopia Contact Us LOGIC DELAY MODULES Background Passive Delay Lines Active Delay Lines Logic Delay Lines Logic Delay Modules "Multi" Logic Delay Lines Programmable Logic Delay Lines Digital Modules Inductors Hall-Effect Sensors

5000ns

Contextual Info: Chapter 8 - Silos III Simulation Chapter 8: Silos III Simulation This chapter is divided into four sections: 8.1 8.2 8.3 8.4 Overview of Silos III Creating Input Stimulus for Simulation Simulating with Silos III Reviewing Simulation Results 8.1 Overview of Silos III

DEM 22 MSDS

Abstract: TGS 823 XPRO 6502 microprocessor
Contextual Info: ModelGen Version 4.3 User Guide Copyright 1999-2001. All rights reserved. ARM DUI 0050F ModelGen User Guide Copyright © 1999-2001. All rights reserved. Release Information Change history Date Issue Change 29 February 2000 C New version created 5 June 2000

Contextual Info: ANLAN203 KSZ84xx GPIO Pin Output Functionality Introduction Devices in Micrel’s ETHERSYNCH family have several GPIO pins that are linked to the internal IEEE 1588 precision time protocol PTP clock. These pins can be individually configured for input or output. This application

Contextual Info: lowprofile t 2l COMPATIBL 4-BIT PROGRAMMABLE LOGIC DELAY LINE # T 2 l input and output # Delays stable and precise # 32-pin D IP package .250 high capacitive, in d u c tiv e and resistive elem ents. # Available in delays up to 765ns these m odules are b u rn e d -in to Level B o f M l L -S T D -8 83 to ensure

35CGQ045

Abstract: diode 5d smd SS5622 single phase full wave rectifier transistor 5d smd SMD Diode 631 ny smd transistor smd transistor 5d smd diode 5d SS555
Contextual Info: Space Level Components Sensitron • 221 West Industry Court · Deer Park, NY 11729-4681 · Phone 631 586 7600 · Fax (631) 242 9798 · World Wide Web - www.sensitron.com · E-mail - sales@sensitron.com 145-0308 Space Level Diodes Sensitron sales@sensitron.com

Contextual Info: lowprofile t 2l COMFATIBL 3-BIT PROGRAMMABLE DELAY LINE INCLUDING INPUT DRIVER _ J T^L input and output Delays stable and precise 16-pin DIP package .2 4 0 high Available in delays up to 357ns when calculated per MIL-HDBK-21 7 fo r a 50°C ground fixed en­