5-101 OS ON Search Results

O10S

Contextual Info: PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD — t PD = 15 ns Features — ts = 8 ns • 384 macnocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes

NAS201

Abstract: RAID-5 NAS401 NAS400 NAS801 hdd agere NAS200 DLNA et1011 USB Streaming Controllers
Contextual Info: Product Brief October 2005 NAS100/101, NAS200/201, NAS400/401, and NAS800/801 Network Attached Storage NAS Server Controllers 1 Introduction to Networked Attached Storage Server Controllers The four NAS device families are system-on-a-chip (SoC) network attached storage (NAS) and media

ml339

Abstract: CY37032VP44-100AI 236Q CY37032V
Contextual Info: UltraLogic 32-Macrocell ISR™ CPLD Features — t PD = 8.5 ns — ts = 5.0 ns • 32 macrocells in two logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tCo - 6.0 ns — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes

2SK2525-01

Contextual Info: S P E C I F I C A T I ON DEVICE NAME : TYPE NAME : Power MOSFET 2 SK 2 5 2 5- 0 I SPEC. No. F u j i E l e c t r i c Co., Ltd. This S p e c ific a tio n is subject to change w ithout notice. DATE NAME APPROVED P • imiîj îi wF il vn yr ut ri wi r CHECKED

Contextual Info: OSLON Black Series 940 nm Lead (Pb) Free Product - RoHS Compliant SFH 4725S DRAFT - This design is for Reference only. Subject to change - may be necessary in a limited number of cases. Wesentliche Merkmale • IR-Lichtquelle mit hohem Wirkungsgrad • 2-fach Stack Emitter

21n60G

Abstract: FMW21N60G 21N60 HER 103 diode
Contextual Info: DATE CHECKED Sep.-27-'04 CHECKED Sep.-27-'04 NAME DWG.NO. Th i s m at er i al and t he i nfo r mat i on her ei n i s t he p r ope r t y of Fuj i El ect r i c C o.,Lt d. They s hal l be nei t her r epr oduced, copi ed, l ent , or d i s cl os e d i n a ny way what s o ev er f or t he us e of any

4053-Q

Abstract: OHF04132
Contextual Info: CHIPLED 850 nm mit hoher Ausgangsleistung CHIPLED® with High Power Infrared Emitter (850 nm) Lead (Pb) Free Product - RoHS Compliant  SFH 4053 DRAFT - This design is for reference only. Subject to change. Wesentliche Merkmale Features • Sehr kleines Gehäuse:

Contextual Info: MITSUBISHI Pch POWER MOSFET FY4ADJ-03A HIGH-SPEED SWITCHING USE FY4ADJ-03A .ill. • 4V DRIVE • V d s s . .-3 0 V rDS ON (MAX) . .80m£2 • Id . .—4A • APPLICATION M otor control, Lamp control, Solenoid control

CY37256P160-125AI

Abstract: 37256P160 ieee1149.1 cypress 37-25615
Contextual Info: fax id: 6148 1Ult ra372 56 PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features • • • • • • • • • Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis

LCMXO256C-3TN100I

Abstract: lattice machxo lcmxo1200c LCMXO1200C-3FTN256I LCMXO2280C-3FTN256I lcmxo640c-3tn100i LCMXO1200 LCMXO256C LVCMOS33 machxo256 LVCMOS15
Contextual Info: Introduction MachXO Family Data Sheet Lattice Semiconductor The devices use look-up tables LUTs and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, highsecurity, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and

O96-I

Contextual Info: fax id: 6149 1Ult ra372 56 V PRELIMINARY Ultra37256V UltraLogic 256-Macrocell 3.3V ISR™ CPLD • Up to 192 I/Os — plus 5 dedicated inputs including 4 clock inputs • Product-term clocking • IEEE1149.1 JTAG boundary scan • Programmable slew rate control on individual I/Os

pnx8320

Abstract: PNX83 DiabData compiler DVP examples dl 750 philips
Contextual Info: Software Architecture and Development Environment for Nexperia pnx8320 Series Home Entertainment Engines Nexperia pnx8320 Software Architecture The Nexperia pnx8320 Home Entertainment Engines, systems-on-a-chip SoCs designed for use in advanced set-top boxes, comply with Philips Nexperia

DI027

Abstract: SI010 DI024 DI028 DI026 SI06 si011 di021
Contextual Info: WH11DXL2X-001X MODULAR WHITE /M ICRO ELECTRO NICS 320C30 M ODULE, 16M SRAM/16M FLASH, ASIC ADVANCED* FEATURES FUNCTIONAL DESCRIPTION • Based on TM S320C 30 DSP ■ ■ Processor C lock Frequencies: 25, 33 M H z The 320C30 D igital Signal Processor M CM is a high perform ance,

p5v3

Abstract: 8Kx32 P5V2
Contextual Info: WH11FXL2X-001X WHITE /M IC R O E L E C T R O N IC S 320C30 M ODULE. 16M SRAM/16M FLASH. FPGA MODULAR ADVANCED* FEATURES FUNCTIONAL DESCRIPTION • Based on TM S320C 30 DSP ■ ■ Processor Clock Frequencies: 25, 33 M H z ■ Integra ted Clock G eneration C irc u itry

Contextual Info: MITSUBISHI Neh POWER MOSFET FS12KMA-4A HIGH-SPEED SWITCHING USE FS12KMA-4A OUTLINE DRAWING D im ensions in mm 10 ±0.3 2.8 ±0.2 4 • 10V DRIVE • V . .200V • rDS ON (M A X ). .0.40Í2

PIC16 example codes spi

Abstract: spi PIC16 example codes PIC16 example code microwire master digital clock using pic16 PIC16 example codes spi MASTER pic16 spi MAX5120 MAX5121 MAX5130 MAX5130AEEE
Contextual Info: 19-1429; Rev 0; 2/99 +3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference The MAX5130/MAX5131 are low-power, 13-bit, voltageoutput digital-to-analog converters DACs with an internal precision bandgap reference and output amplifier. The MAX5130 operates on a single +5V supply with an

16N60G

Abstract: HER 107 diode HER 103 diode FMW16N60G 16N60
Contextual Info: DATE CHECKED Jun.-01-'05 CHECKED Jun.-01-'05 NAME DWG.NO. Th i s m at er i al and t he i nfo r mat i on her ei n i s t he p r ope r t y of Fuj i El ect r i c C o.,Lt d. They s hal l be nei t her r epr oduced, copi ed, l ent , or d i s cl os e d i n a ny way what s o ev er f or t he us e of any

GT280

Abstract: GT150
Contextual Info: 12 10 1 1 9 i 7 6 5 SYMBOL DEFINITION A DIMENSION WITHOUT AN INSPECTION REPORT SYMBOL DOES NOT REQUIRE INSPECTION. IT MAY BE CONTROLLED ON AN INDIVIDUAL COMPONENT DRAWING H 4 MISSING NUMBERS TOTAL NO. OF SYMBOLS ON DRAWING 20 LAST NO. USED 25 2 3 DWG STATUS

PIC16Fxxx

Abstract: architecture mcu flash disk PIC17c756A assembly programming MPLAB-C18 PIC18CXXX CAN protocol basics embedded c programming examples immobilizer protocol how is the burglar alarm system work PIC17C7XX
Contextual Info: A Comprehensive Guide to Microchip Technology’s Hands-On Technical Training Hands-On Technical Workshops PICMICRO MCU device families • KEELOQ® Security Products Microchip’s Hands-On Technical Workshops Will Show You How To Push Your Designs to the Limit. . .

CY37256

Abstract: CY37256V O116
Contextual Info: Back PRELIMINARY CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • •

CY37256

Abstract: CY37256V
Contextual Info: PRELIMINARY CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • •

Contextual Info: 7? tv u J 6 olZ'&Q. . —/ _ SÌ99S8DY Dual Enhancement-Mode MOSFET N- and P- Channel Product Summary V d s (V) N-Channel 20 P-Channel -20 I d (A) ±3.5 ±3 ±2.5 ±3.5 ±3 ±2.5 rDS(on) (&) 0.10 @ VGS = 10 v 0.12 @ VGs = 6 V

TEA 1112 A

Abstract: TCS101
Contextual Info: Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Features — tco = 4 .5 ns • Product-term clocking • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes

fototransistor

Contextual Info: 2013-08-14 Infrared-Emitter 850 nm and Si-Phototransistor IR-Emitter (850 nm) und Si-Fototransistor Version 1.0 SFH 7250 Features: Besondere Merkmale: • Available on tape and reel • SMT package with IR emitter (850 nm) and Si-phototransistor • Suitable for SMT assembly