470PS Search Results

LV33

Abstract: AZ100LVEL33 AZ100LVEL33D AZ100LVEL33NG AZ100LVEL33T AZ10LVEL33 AZ10LVEL33D AZ10LVEL33T AZM10 MC100EL33
Contextual Info: ARIZONA MICROTEK, INC. AZ10LVEL33 AZ100LVEL33 ECL/PECL ÷4 Divider PACKAGE AVAILABILITY FEATURES • • • • • • • • PACKAGE Green / RoHS Compliant / Lead Pb Free package available Operating Range of 3.0V to 5.5V 470ps Propagation Delay 4.0GHz Toggle Frequency

AZ100LVEL32DG

Abstract: AZ100LVEL32NG AZ100LVEL32TG AZ10LVEL32 LV32 4020 divider
Contextual Info: ARIZONA MICROTEK, INC. AZ10LVEL32 AZ100LVEL32 PACKAGE AVAILABILITY FEATURES • • • • • ECL/PECL ÷ 2 Divider Operating Range of 3.0V to 5.5V 470ps Propagation Delay 3.0GHz Toggle Frequency High Bandwidth Output Transitions Direct Replacement for ON

Contextual Info: CTS100LVEL32 LVPECL Divide by 2 Divider MLP8, MSOP8, SOIC8 Features Block Diagram 3.0+ GHz Toggle Frequency 470ps Propagation Delay Internal Input Pull-down Resistors 3.0V to 5.5V Power Supply  RoHS Compliant Pb Free Packages     Description

AZ100LVEL33

Abstract: AZ10LVEL33 AZ10LVEL33D AZ10LVEL33DR1 AZ10LVEL33DR2 MC100EL33 MC100LVEL33 MC10EL33
Contextual Info: ARIZONA MICROTEK, INC. AZ10LVEL33 AZ100LVEL33 ECL/PECL ÷4 Divider PACKAGE AVAILABILITY FEATURES • • • • • • Operating Range of 3.0V to 5.5V 470ps Propagation Delay 4.0GHz Toggle Frequency Internal Input Pulldown Resistors Direct Replacement for ON Semiconductor

MC10EL33

Abstract: AZ100LVEL33 AZ100LVEL33NG AZ10LVEL33 AZM10 MC100EL33 MC100LVEL33
Contextual Info: ARIZONA MICROTEK, INC. AZ10LVEL33 AZ100LVEL33 ECL/PECL ÷4 Divider PACKAGE AVAILABILITY FEATURES • • • • • • • • PACKAGE Green / RoHS Compliant / Lead Pb Free package available Operating Range of 3.0V to 5.5V 470ps Propagation Delay 4.0GHz Toggle Frequency

HL33G

Contextual Info: CTS100LVEL33 LVPECL Divide by 4 Divider MLP8, MSOP8, SOIC8 Features Block Diagram 5.0+ GHz Toggle Frequency 470ps Propagation Delay Internal Input Pull-down Resistors 3.0V to 5.5V Power Supply  RoHS Compliant Pb Free Packages     Description

tc183

Abstract: E17G tc183G TC163G TC180G single port RAM TC183e Toshiba TC8570
Contextual Info: TOSHIBA TC183G/ECMOS ASIC Family 3.0V/3.3V and 5.0V, 0.5nm1 TheTC183G/E eases the transition from 5V to 3V based systems. Benefits • Mixed 3.0/3,3V and 5V I/O 0.5 micron CMOS process with fast 230ps gate delay performance with the power savings of a 3V core

EB-RD35

Abstract: GS9008 GS9024 GS9025 GS9028 GS9028-CKA GS9028-CTA
Contextual Info: GENLINX II GS9028 Cable Driver with Two Adjustable Outputs DATA SHEET FEATURES DESCRIPTION • SMPTE 259M compliant The GS9028 is a second generation bipolar integrated circuit designed to drive two 75Ω co-axial cables. • operational from DC to 622Mb/s

CXB1565R

Contextual Info: CXB1565R 622Mbps Clock & Data Recovery with High Sensitivity Limitting Amplifier For the availability of this product, please contact the sales office. Description The CXB1565R achieves 3R optical-fiber communication receiver functions Reshaping and Regenerating

Contextual Info: SONY CXB1565R 622Mbps Clock & Data Recovery with High Sensitivity Limitting Amplifier Description The CXB1565R achieves 3R optical-fiber commu­ nication receiver functions Reshaping and Regenerating and Retiming on a single chip. This IC also equipped with the signal interruption alarm output, which is

0B11-R

Abstract: 21PAD
Contextual Info: ADVANCE‡ 21PAD HOST CONTROLLER 21 PAD Host Controller MT8LLN21PADF For the latest data sheet please refer to the Micron Web site: www.micron.com/chipset. FEATURE OVERVIEW • Supports up to two Intel Pentium III® [80533/ 80530 family] at 133 MHz front side bus frequency

TC180G21

Abstract: single port ram TC180 TC180G TC160G AM 770 DENSITY TRANSMITTER Toshiba NAND 67 Bga tc8565 toshiba graphics tc183G
Contextual Info: TOSHIBA TC180 Series CMOS ASIC Family 3.0V/3.3V, 0.5nm1 The TC180 series increases system performance and device integration while reducing power. Benefits • True 3.0/3,3V 0.5 micron CMOS process with fast 230ps gate delays • Reduced power consumption makes lower cost plastic packag­

TC180G21

Abstract: TC180G TC160G single port RAM TC180 0724 XBRL16 toshiba ASIC
Contextual Info: TOSHIBA TC180 Series CMOS ASIC Family 3.0V/3.3V, 0.5nm1 The TC180 series increases system performance and device integration while reducing power. Benefits • True 3.0/3.3V 0.5 micron CMOS process with fast 230ps gate delays • Reduced power consumption makes lower cost plastic packag­

7301B

Abstract: 162MHz 7301A CH7009B
Contextual Info: CH7009/CH7301 Chrontel CHRONTEL CHRONTEL CHRONTEL Technical Bulletin 41 DVI OUTPUT EYE DIAGRAMS OF CH7009A/7301A VS. CH7009B/7301B Scope CH7009B/7301B, which are the successors of CH7009A/7301A, are fully DDWG compliant DVI transmitters. The new chips are able to transmit DVI display data from 25MHz up to 165 MHz pixel clocks. CH7009A/7301A

SY89473U

Abstract: SY89474U SY89474UMG SY89474UMGTR SY89840U SY89845U MLF24
Contextual Info: SY89474U Precision LVDS 2:1 Multiplexer with 1:2 Fanout and Internal Termination General Description The SY89474U is a 2.5V precision, high-speed 2:1 differential MUX capable of processing clocks up to 2.5GHz and data up to 2.5Gbps. The differential input includes Micrel’s unique, 3-pin input

Contextual Info: >ONY |_ CXB1565R 622Mbps Clock & Data Recovery with High Sensitivity Limitting Am plifier Description The CXB1565R achieves 3R optical-fiber commu­ nication receiver functions Reshaping and Regenerating and Retiming on a single chip. This IC also equipped

Contextual Info: SY89833AL 3.3V Low Noise Ultra-Precision 1:4 LVDS Fanout Buffer/Translator with Internal Termination General Description The SY89833AL is a lower noise version of the SY89833L 3.3V, high-speed 2GHz Low Voltage Differential Swing LVDS 1:4 fanout buffer. Within device skew is

GS9028-CKA

Abstract: GS9028-CTA EB-RD35 GS9008 GS9024 GS9028 GS9028CKAE3
Contextual Info: GENLINX II GS9028 Cable Driver with Two Adjustable Outputs DATA SHEET FEATURES DESCRIPTION • SMPTE 259M compliant The GS9028 is a second generation bipolar integrated circuit designed to drive two 75Ω co-axial cables. • operational from DC to 622Mb/s

can transceiver lumped capacitance

Abstract: GTO Driver DS91C176 DSAE001816
Contextual Info: Lumped vs TLine Simulation Study Interface Products January 2003 1 This simulation study compares a LVCMOS output driving a lumped cap load vs. various length transmission lines. The goal of this study was to determine at what length does the line act as a

Contextual Info: CXB1565R 622Mbps Clock & Data Recovery with High Sensitivity Limitting Amplifier Description The CXB1565R achieves 3R optical-fiber communication receiver functions Reshaping and Regenerating and Retiming on a single chip. This IC also equipped with the signal interruption alarm output, which is

Contextual Info: SY89833AL 3.3V Low Noise Ultra-Precision 1:4 LVDS Fanout Buffer/Translator with Internal Termination General Description The SY89833AL is a lower noise version of the SY89833L 3.3V, high-speed 2GHz Low Voltage Differential Swing LVDS 1:4 fanout buffer. Within device skew is

MIC284x

Abstract: 8873m KSZ8873MLL Power line load switch for portable dvd china KSZ8873 MIC2844 china DVD player card circuit diagram MIC2164 SY89833AL micrel tx battery 3v
Contextual Info: Q2 2009 Volume 35 Micrel Inc., is a leading global manufacturer of IC solutions for the worldwide analog, Ethernet and highbandwidth markets. The Company’s Micrel New Product Highlights products include advanced mixedsignal, analog and power semiconductors; high performance

Contextual Info: GENLINX II GS9028 Cable Driver with Two Adjustable Outputs PRELIMINARY DATA SHEET FEATURES DESCRIPTION • SMPTE 259M compliant The GS9028 is a second generation bipolar integrated circuit designed to drive two 75Ω co-axial cables. • operational from DC to 622Mb/s

AZ100LVEL32

Abstract: ECL divider marking C2G
Contextual Info: AZ100LVEL32 PECL/ECL ÷2 Divider www.azmicrotek.com FEATURES DESCRIPTION • • • The AZ100LVEL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the