44107 Search Results

44107

Abstract: MC44107P
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 44107 Product Preview IR R em ote Control T ransm itter CMOS P SUFFIX The M C 44107 rem ote control tra n sm itte r co nve rts a keyboard input into a pulse code m odulated signal suitable for infrared transm ission to an a ppropriate

BSC 68H

Abstract: SCK 055 TSOP 28 SPI memory Package flash AT45DB161 AT45DB161B AT45DB161-CC AT45DB161-RC PA10 PA11 AT45DB161-TC
Contextual Info: Features • • • • • • • • • • • • • • • 100% Compatible to AT45DB161 Single 2.7V - 3.6V Supply Serial Interface Architecture Page Program Operation – Single Cycle Reprogram Erase and Program – 4096 Pages (528 Bytes/Page) Main Memory

DMX RECEIVER

Abstract: TEMPERATURE CONTROLLER with pid AVR pid 420 f9001 93F2330 PID code for avr circuit diagram of pid controller DMX chip PC keyboard CIRCUIT diagram AT43USB324 PANASONIC ECEV1AA101SP
Contextual Info: Features • • • • • • • • • • • • • • • AVR 8-bit RISC Microcontroller with 83 ns Instruction Cycle Time USB Hub with One Attached and Two External Ports USB Keyboard Function with Three Endpoints 16K Bytes of Program Memory, 512 Bytes SRAM

AT45D161

Abstract: AT45DB161B TSOP 28 SPI memory Package flash AT45D161-JC PA10 PA11
Contextual Info: Features • Single 4.5V - 5.5V Supply • Serial Interface Architecture • Page Program Operation • • • • • • • • • • • – Single Cycle Reprogram Erase and Program – 4096 Pages (528 Bytes/Page) Main Memory Optional Page and Block Erase Operations

AT90SC6464C

Abstract: AT90SC3232 AT90SC 8-bit AVR AT90SC1616C AT90SC3232C ATMEL serial EEPROM 32K atmel at90sc
Contextual Info: Features • High-performance, Low-power 8-bit AVR RISC Architecture • • • • • • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution Up to 64K Bytes Flash Program Memory – Endurance: 10K Write/Erase Cycles

Contextual Info: Features • • • • • • • Basic CAN Cell Fully Compliant with CAN standard Rev 2.0 B Automatic Reply 1 Mbit/s Maximum Transfer Rate Fully Scanable 99% Fault Coverage Gate Count: Approximately 2800 Gates Description The Controller Area Network CAN is a serial communications protocol. The CAN

lv8011

Abstract: AT49BV8011 AT49BV8011T AT49LV8011 AT49LV8011T
Contextual Info: Features • Single Supply for Read and Write: 2.7V to 3.3V BV , 3.0V to 3.3V (LV) • Access Time – 90 ns • Sector Erase Architecture • • • • • • • • • • • Fourteen 32K Word (64K Byte) Sectors with Individual Write Lockout Two 16K Word (32K Byte) Sectors with Individual Write Lockout

AT45DB161-RI

Abstract: AT45DB161 AT45DB161-JC atmel 528 AT45DB161B PA10 PA11 AT45DB161-TC
Contextual Info: Features • Single 2.7V - 3.6V Supply • Serial Interface Architecture • Page Program Operation • • • • • • • • • • • – Single Cycle Reprogram Erase and Program – 4096 Pages (528 Bytes/Page) Main Memory Optional Page and Block Erase Operations

AT17

Abstract: AT17LV040 AT24CXXX AT40K ATDH2200E XC3000 XC4000 XC5200 AT17C
Contextual Info: Features • EE reprogrammable 4,194,304 x 1 bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • In-System Programmable via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX Devices,

496k

Abstract: AT49F008A-90TI AT49F008A AT49F008AT AT49F8192A AT49F8192AT
Contextual Info: Features • Single-voltage Operation • • • • • • • • • – 5V Read – 5V Programming Fast Read Access Time – 90 ns Internal Erase/Program Control Sector Architecture – One 8K Word 16K Bytes Boot Block with Programming Lockout – Two 4K Word (8K Bytes) Parameter Blocks

LV010

Abstract: LV020 ATMEL EEPROM 256 AT17C LV002
Contextual Info: Programming Atmel’s EEPROMs: AT17C/LV020 A vs. AT17C/LV002(A) Features • Major Differences in Programming the AT17C/LV020(A) and the AT17C/LV002(A) EEPROMs • Internal Structure of the AT17C/LV020(A) and the AT17C/LV002(A) EEPROMs Introduction This application note provides Atmel’s customers with a description of the major

circuit diagram of Tri-State Buffer using CMOS

Abstract: verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart
Contextual Info: Features • 0.5 µm Drawn Gate Length 0.45 µm Leff Sea-of-Gates Architecture with • • • • • Triple-level Metal Embedded E2 Memory up to 256 Kb 3.3V Operation with 5.0V Tolerant Input and Output Buffers High-speed, 200 ps Gate Delay, 2-input NAND, FO = 2 Nominal

AT49LV040

Abstract: 496k AT49BV040 AT49LV040-70TC AT49BV040-12JC
Contextual Info: Features • • • • • • • • • Single Voltage for Read and Write: 2.7V to 3.6V BV , 3.0V to 3.6V (LV) Fast Read Access Time – 70 ns Internal Program Control and Timer 16K Bytes Boot Block with Lockout Fast Chip Erase Cycle Time – 10 seconds

atmel 8052 PIN CONFIGURATION

Abstract: atmel 8052 microcontroller atmel 8052 8052 atmel AT89 1106C 80C51 80C52 AT87F51RC MCS-51
Contextual Info: Features • • • • • • • • • • • • • • • Compatible with MCS-51 Products 32K Bytes of One-time Programmable QuickFlash™ Memory 4V to 6V Operating Range Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock

AT24CXXX

Abstract: atmel 1050 AT17 AT17C010 AT90S8515 AT17CXXX
Contextual Info: Industry-standard 2-wire Protocol “Bit-banged” C Routines for the AVR Microcontroller/ISP Code for the AT17CXXX FPGA Configuration Memories Features • C Routines for Serial Interface • Example Circuit for AVR Programming • • • • FPGA Configuration Memories

SMT6T15CA

Abstract: AT91M55800 diode b27 AT49BV16X4 AT91EB55 AT91M55800A qtz xtal sck 053 fuse box header 2x10 right angle AE20 DIODE
Contextual Info: AT91EB55 Evaluation Board . User Guide Table of Contents Section 1 Overview. 1-1 1.1 1.2

AT40K

Abstract: AT94K ubrof
Contextual Info: Getting Started with C for the FPSLIC Family Using the IAR Compiler Features • • • • • How to Open a New Project Description of Option Settings Linker Command File Examples Writing and Compiling the C Code How to Load the Debug and Executable

GE133

Abstract: cdva AT75C AT75C220 AT75C320 GT Plus Oncore "vector instructions" saturation FS Oncore
Contextual Info: Features • • • • • • • • • • • Fully Autonomous DSP System 16-bit Fixed-point OakDSPCore 24K x 16 of Uploadable Program RAM 16K x 16 of Data RAM 2K x 16 of X-RAM 2K x 16 of Y-RAM X-RAM and Y-RAM Accessible within the Same Cycle JTAG Interface Available on AT75C220 and AT75C320

AT91M63200-25AI

Abstract: AT91M63200 D786
Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb Processor Core • • • • • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In-circuit Emulation

AT40K

Abstract: AT94K
Contextual Info: Getting Started with ImageCraft C for the FPSLIC™ Family Features • How to Open a New Project • Description of Option Settings • Writing and Compiling the C Code Introduction The purpose of this application note is to guide new users through the initial settings of the ImageCraft IDE and compile

sam9793

Abstract: Equalizer delay reverb reverb IC 1N4148 MPU-401
Contextual Info: Features • Synthesizer, Reverb, Chorus on a Single Chip • No External ROM or RAM • Single-chip All-in-one Design, Only Requires External DAC • • • • • • – MIDI Control Processor, Serial and Parallel Interface – Synthesis – Compatible Effects: Reverb and Chorus

Contextual Info: Features • • • • Edge-controlled Power-down Pin Zero Power Equivalent of ATF20V8B Edge-sensing Zero Standby Power 10 |aA Typical Industry Standard Architecture - Emulates Many 24-pin PALs - Low-cost Easy-to-use Software Tools High-speed Electrically-erasable Programmable Logic Devices

Contextual Info: Features Advanced, High-speed Programmable Logic Device - Superset of 22V10 - Improved Performance - 7.5 ns tPD, 95 MHz External Operation - Enhanced Logic Flexibility - Backward Compatible with ATV750/L Software and Hardware New Flip-flop Features - D- or T-type

Contextual Info: Features • Operates Between 2.7V to 5.5V • High-density, High-perform ance Electrically-erasable Complex Programmable Logic Device - 44-pin, 32 I/O CPLD - 12 ns Maximum Pin-to-pin Delay - Registered Operation Up To 90.9 MHz - Fully Connected Input and Feedback Logic Array