4050 SPICE Search Results

marking CODE D2B

Abstract: ic 4050 pin diagram
Contextual Info: MC100E256 5V ECL 3-Bit 4:1 Mux-Latch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

socket 775 pinout

Abstract: PLCC28 package
Contextual Info: MC100E193 5V ECL Error Detection/ Correction Circuit The MC100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

Contextual Info: MC100E336 5V ECL 3-Bit Registered Bus Transceiver The MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0−BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 − Q2) are specified for 50 Ω.

Contextual Info: MC100E337 5V ECL 3-Bit Scannable Registered Bus Transceiver The MC100E337 is a 3-bit registered bus transceiver with scan. The bus outputs BUS0−BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 − Q2) are specified for 50 Ω. The bus outputs feature a normal

transistor Bd 575

Contextual Info: MC10E212, MC100E212 5V ECL 3-Bit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to

4050 spice

Abstract: a7634
Contextual Info: SPICE Device Model SUU/SUD50N04-08P Vishay Siliconix N-Channel 40-V D-S 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range

AN1404

Abstract: AN1405 AND8020 MC100E256 MC100E256FN MC100E256FNR2
Contextual Info: MC100E256 5V ECL 3-Bit 4:1 Mux-Latch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

AND8020

Abstract: E141 E241 MC100E241 MC100E241FN MC100E241FNR2 marking code e141
Contextual Info: MC100E241 5VĄECL 8ĆBit Scannable Register The MC100E241 is an 8-bit shiftable register. Unlike a standard universal shift register such as the E141, the E241 features internal data feedback organized so that the SHIFT control overrides the HOLD/LOAD control. This enables the normal operations of HOLD

Contextual Info: MC100E193 5V ECL Error Detection/ Correction Circuit The MC100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

AN1404

Abstract: AN1405 AND8020 MC100E256 MC100E256FN MC100E256FNR2 D2D marking code
Contextual Info: MC100E256 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

MC100E101

Abstract: MC100E101FN MC100E101FNR2 MC10E101 MC10E101FN MC10E101FNR2
Contextual Info: MC10E101, MC100E101 5VĄECL Quad 4ĆInput OR/NOR Gate The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V • http://onsemi.com

3525 "application note"

Abstract: SECDED ic 4050 AN1404 AND8020 E160 MC100E193 MC100E193FN MC100E193FNR2 socket 775 pinout
Contextual Info: MC100E193 5VĄECL Error Detection/ Correction Circuit The MC100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

AN1404

Abstract: AN1405 AND8020 MC100E336 MC100E336FN MC100E336FNR2
Contextual Info: MC100E336 5VĄECL 3ĆBit Registered Bus Transceiver The MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0–BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω.

AN1404

Abstract: AN1405 AND8020 MC100E336 MC100E336FN MC100E336FNR2
Contextual Info: MC100E336 5V ECL 3-Bit Registered Bus Transceiver The MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0−BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 − Q2) are specified for 50 Ω.

Contextual Info: MC100E241 5V ECL 8-Bit Scannable Register The MC100E241 is an 8-bit shiftable register. Unlike a standard universal shift register such as the E141, the E241 features internal data feedback organized so that the SHIFT control overrides the HOLD/LOAD control. This enables the normal operations of HOLD

E212 transistor

Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

marking CODE D2B

Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

MC100E163

Abstract: MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2
Contextual Info: MC10E163, MC100E163 5VĄECL 2ĆBit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 – A7, B0 – B7) is propagated to the output.

MC100E154

Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
Contextual Info: MC10E154, MC100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on

E112

Abstract: E212 MC100E212 MC100E212FN MC100E212FNR2 MC10E212 MC10E212FN MC10E212FNR2 E212 transistor
Contextual Info: MC10E212, MC100E212 5VĄECL 3ĆBit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to

MC100E157

Abstract: MC100E157FN MC100E157FNR2 MC10E157 MC10E157FN MC10E157FNR2
Contextual Info: MC10E157, MC100E157 5VĄECL Quad 2:1 Multiplexer The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.

MC100E167

Abstract: 100E167 MC100E167FN MC100E167FNR2 MC10E167 MC10E167FN MC10E167FNR2
Contextual Info: MC10E167, MC100E167 5VĄECL 6ĆBit 2:1 MuxĆRegister The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop

Contextual Info: SPICE MODEL: MBRM5100H MBRM5100H 5A HIGH VOLTAGE SCHOTTKY BARRIER RECTIFIER POWERMITEÒ3 UNDER DEVELOPMENT NEW PRODUCT Features • · · · · · Guard Ring Die Construction for Transient Protection High Surge Current Capability Very Low Leakage Current High Junction Temperature Capability

Contextual Info: SPICE MODEL: MBRM5100H MBRM5100H 5A HIGH VOLTAGE SCHOTTKY BARRIER RECTIFIER POWERMITEÒ3 UNDER DEVELOPMENT NEW PRODUCT Features • · · · · · Guard Ring Die Construction for Transient Protection High Surge Current Capability Very Low Leakage Current High Junction Temperature Capability