402B Search Results

"AWM Style 20726"

Abstract: 802BY00011 602BY00001 502BY00011 682by00011 "AWM Style 20726 202BY00010 242BY00002 madison 642BY00001
Contextual Info: MULTI-CONDUCTOR 30 AWG 0.025” CENTER FLAT CABLE Major Diameter 0.024 +/- 0.003" Blue Edge Mark 0.025 +/- 0.002" 362BY00001 0-1284063-1 36 0.900 402BY00010 0-1284064-1 40 1.000 442BY00001 0-1284065-1 44 1.100 502BY00011 5-1219763-0 50 1.250 602BY00001 0-1284066-1

Y-402B

Abstract: 402B
Contextual Info: Two Electrode Gas Tube Surge Arrester Part Number: Y-402B Features: 30 ± 2.0 0.8 Units: mm 8.5 ± 0.3 Applications: 30 ± 2.0 Marking Transient Voltage Surge Suppression (TVSS) AC Line Input Protection Power Supplies CATV Systems Antennas Digital Satellite Systems (DSS)

80C452-1

Abstract: DIA DB3
Contextual Info: ’r INTEL CORP UP/PRPHLS intgl 31E D ~ ' - -r.-' • 402bli7S OQfl'ifim 5 ■ 9 r - ? 2 - 3 Z - ir UPI-452 CHMOS PROGRAMMABLE I/O PROCESSOR 83C452 - 8K x 8 Mask Programmable Internal ROM 80C452-External ROM/EPROM 83C452/80C452:3.5 to 14 MHz Clock Rate Software Compatible with the MCS-51

HEM402

Abstract: hp 8060
Contextual Info: H 402B /H EM 402B ABOWEI B ro a d b a n d V C O BO W EI INTEG RATED C IR C U IT S C O .,L T D . Typical Performance Features • Low phase noise • H yperabrupt varactor octave bandwidth • Perfect tuning linearity • R eliable thin film hybrid construction

qimonda

Abstract: hyb18t2g802bf-3s
Contextual Info: January 2007 HYB18T 2G 402B F HYB18T 2G 802B F 2 - G b i t D u a l D i e D o u b l e - D a t a - R a t e - T w o SD R A M DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.0 Internet Data Sheet HYB18T2G[4/8]02BF–[3S/3.7/5] 2-Gbit Dual Die Double-Data-Rate-Two SDRAM

HYB18T2G802BF

Abstract: HYB18T2G802BF-3
Contextual Info: November 2007 HYB18T 2G 402B F HYB18T 2G 802B F 2 - G b i t D u a l D i e D o u b l e - D a t a - R a t e - T w o SD R A M DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.10 Date: 2007-11-05 Internet Data Sheet HYB18T2G[40/80]2BF 2-Gbit Dual Die Double-Data-Rate-Two SDRAM

Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SC LS 402B - A P R IL 1998 - R EVISED JULY 1998 EPIC Enhanced-Performance Implanted CMOS Process SN54LV165A . . . J OR W PACKAGE SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) Typical V q lp (Output Ground Bounce)

C-48U

Abstract: 2N3739 QML-19500 C48U TO-66 CASE 614
Contextual Info: This documentation process conversion measures necessary to comply with this revision shall be completed by 30 October 1999. INCH-POUND MIL-PRF-19500/402C 30 August 1999 SUPERSEDING MIL-S-19500/402B 8 April 1993 PERFORMANCE SPECIFICATION SHEET SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, POWER

80188

Abstract: intel 80188
Contextual Info: INTEL CORP UP/PRPHLS m 44E D 402bl7S D'lDSB?*! 7 B I T L 1 T 'Y ? '/ 7 '0 7 80188 HIGH INTEGRATION 8-BIT MICROPROCESSOR Integrated Feature Set — Enhanced 8086-2 CPU — Clock Generator — 2 Independent DMA Channels — Programmable Interrupt Controller'

Contextual Info: HN62454 Series 262144-word x 16-bit/524288-word x 8-bit CMOS Mask Programmable ROM HITACHI ADE-203-402B Z Rev. 2.0 Jun. 26, 1997 Description The Hitachi HN62454 series is a 4-Mbit CMOS mask programmable ROM organized either as 262144word x 16-bit or as 524288-word x 8-bit. As it has realized high speed normal access 100 ns, it is the most

Contextual Info: in te l 28F020 2048K 256K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 2 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 jas Typical Byte-Program — 4 Second Chip-Program 100,000 Erase/Program Cycles 12.0V ± 5 % Vpp High-Performance Read

Contextual Info: P W iy iM D K M W in tJ . 87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51/80C51BH/80C51BHP/80C31BH "See Table 1 for Proliferation Options High Performance CHMOS EPROM 5 Interrupt Sources 24 MHz Operation Programmable Serial Port

Contextual Info: ^ EXUKDTT [PIRilMlG inte* 87C196KT/87C196KS 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER Automotive —40°C to + 125°C Ambient High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip EPROM Up to 1 Kbyte of On-Chip Register RAM Up to 512 Bytes of Additional RAM

Contextual Info: I P ^ iU ö Ä Ä f in te i 28F008SA 8-MBIT 1-MBIT x 8 F la s h F ile T M MEMORY Extended Temperature Specifications Included High-Density Symmetrically Blocked Architecture — Sixteen 64-Kbyte Blocks Very High-Performance Read — 85 ns Maximum Access Time

Contextual Info: intJ. 2-MBIT 128K x 16, 256K x 8 LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B, 28F002BL-T/B m Low Voltage Operation for Very Low Power Portable Applications — Vcc = 3.0V-3.6 V • Automatic Power Savings Feature — 0.8 mA Typical Ice Active Current in

Contextual Info: in tj, 8XC196KC/8XC196KC20 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 87C196KC—16 Kbytes of On-Chip OTPROM 83C196KC—16 Kbytes ROM 80C196KC—ROMIess • 16 and 20 MHz Available ■ Dynamically Configurable 8-Bit or 16-Bit Buswidth ■ 488 Byte Register RAM

Contextual Info: intJ 82078 64 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER — Selectable Boot Drive — Standard IBM and ISO Format Features — Format with Write Command for High Performance in Mass Floppy Duplication • Small Footprint and Low Height Packages ■ Supports Standard 5.0V as well as Low

Contextual Info: 80960RP 1.0 1.2 ABOUT THIS DOCUMENT Terminology In this document, the following terms are used: This data sheet contains ADVANCE INFORMATION about Intel’s i960 RP processor, including a func­ tional overview, mechanical data package signal locations and simulated thermal characteristics ,

51FFH

Contextual Info: in te i 82092AA PCI TO PCMCIA/ENHANCED-IDE CONTROLLER • Provides the Ultimate Plug and Play Solution fo r High Perform ance PCI Desktop Systems — Supports Combinations of PCMCIA and Enhanced Local Bus IDE Interfaces — Contains a 32-bit PCI Local Bus

Contextual Info: [PIM2>[E U T P^E^OO in te i 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Binary Compatible with Other80960 Processors • Two Instructions/Clock Sustained Execution 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

intel 27010 eprom

Contextual Info: INTEL CORP Intel* MEMORY/LOGIC 50E D • 4fiS bl7b O O b t Ja M l4 5 ■ /3 -2 9 27010 1M (128K x 8) BYTE-WIDE EPROM ■ Compatible with 28-Pin JEDEC EPROMs: 27256, 27512 ■ Complete Upgrade Capability — PGM “Don’t Care” Status Allows Wiring in Higher Order Addresses

Contextual Info: in te i 80C186EC/80C188EC AND 80L186EC/80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS • Fully Static Operation H True CMOS Inputs and Outputs ■ Integrated Feature Set: — Low-Power, Static, Enhanced 8086 CPU Core — Two Independent DMA Supported

Contextual Info: in tó l. M80C51FB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Mffltary M80C51FB — 3.5 MHz to 12 MHz, VCC = 5V ± 10% M80C51FB-16 — 3.5 MHz to 16 MHz, Vcc = 5V +10% High Performance CHMOS EPROM 32 Programmable I/O Lines Three 16-Bit Timer/Counters 7 Interrupt Sources