4-BIT REGISTER WITH TRUTH TABLE Search Results

224 J

Abstract: 54HC 54LS 74HC 74LS C1995 MM54HC195 MM54HC195J MM74HC195 MM74HC195J
Contextual Info: MM54HC195 MM74HC195 4-Bit Parallel Shift Register General Description trol input is high Serial data for this mode is entered at the J-K inputs These inputs allow the first stage to perform as a J-K or TOGGLE flip flop as shown in the truth table The 54HC 74HC logic family is functionally as well as pinout compatible with the standard 54LS 74LS logic family

W942508BH-6

Abstract: W942508BH W942516AH W942516BH
Contextual Info: W942508BH-6 8M x 4 BANKS × 8 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

W942504AH

Abstract: W942508AH W942516AH
Contextual Info: Preliminary W942504AH 16M x 4 BANKS × 4 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

W942508AH

Abstract: W942516AH
Contextual Info: Preliminary W942516AH 4M x 4 BANKS × 16 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

W942508BH

Abstract: W942516BH W942516BH-6
Contextual Info: W942516BH-6 4M x 4 BANKS × 16 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

E0600

Abstract: MACH210 P16H8 binary to bcd decoder 4 digit COUNTER LED bcd 7449 BCD to 7-segment 7449 decoder and seven segment display 7449 7-segment decoder logic diagram IF-6-24 EP600
Contextual Info: ABEL-HDL Reference Table of Contents 1. Introduction 2. Language Structure Summary . . . . . . . . . . . . . . . . . . . . Introduction to ABEL-HDL . . . . . . . . . . Basic Syntax . . . . . . . . . . . . . . . . . . Supported ASCII Characters . . . . . . .

binary to bcd decoder

Abstract: LT 543 7-segment display PAL Decoder 16L8 MACH210 P16R4 P22V10 EP600 P16V8S 7 SEGMENT DISPLAY LT 543 PIN CONFIGURATION diagram ABEL-HDL Reference Manual
Contextual Info: ABEL-HDL Reference Table of Contents 1. Introduction 2. Language Structure Summary . . . . . . . . . . . . . . . . . . . . Introduction to ABEL-HDL . . . . . . . . . . Basic Syntax . . . . . . . . . . . . . . . . . . Supported ASCII Characters . . . . . . .

pn sequence generator using d flip flop

Abstract: pn sequence generator using jk flip flop FULL SUBTRACTOR using 41 MUX full subtractor circuit using xor and nand gates verilog code for 16 bit carry select adder verilog code pipeline ripple carry adder verilog code for jk flip flop vhdl for 8 bit lut multiplier ripple carry adder synchronous updown counter using jk flip flop Mux 1x8 74
Contextual Info: 0373f.fm Page 1 Tuesday, May 25, 1999 8:59 AM Table of Contents Component Generators Introduction .3 AT40K Co-processor FPGAs .4

Contextual Info: W9464G6IH 1M x 4 BANKS × 16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

W9412G6CH

Abstract: a06 transistor DDR266 DDR333 DDR400 DDR444
Contextual Info: W9412G6CH 2M x 4 BANKS × 16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

W9425G6JH

Contextual Info: W9425G6JH 4 M  4 BANKS  16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

Contextual Info: W9464G6KH 1M  4 BANKS  16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

Contextual Info: HIGH-SPEED 3.3V 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH SEMAPHORE CONTROLS Integrated Device Technology, Inc. ADVANCED IDT70V728S/L FEATURES: DESCRIPTION: • 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Eight independent 8K x 16 banks -1 Megabit of memory on chip

Contextual Info: HIGH-SPEED 32K X 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH SEMAPHORE CONTROLS Integrated Device Technology, Inc. ADVANCED 1DT70727S/L FEATURES: DESCRIPTION: • 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Eight independent 4K x 16 banks - 512 Kilobits of memory on chip

Contextual Info: Integrated Device Technology, Inc. HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH SEMAPHORE CONTROLS ADVANCED 1DT70728S/L FEATURES: DESCRIPTION: • 64K x 16 Bank-Switchable Dual-Ported SRA Architecture - Eight independent 8K x 16 banks -1 Megabit of memory on chip

Contextual Info: DS25CP104 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization General Description The DS25CP104 is a 3.125 Gbps 4x4 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal

Contextual Info: HIGH-SPEED 32K x 16 BANK-SWITCH ABLE DU AL-PORTE D SRAM WITH SEMAPHORE CONT ROLS ADVANCED IDT70727S/L FE ATURES: DESCRIPTION: • 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Eight independent 4K x 16 banks - 512 Kilobits ot memory on chip • Fast asynchronous address-to-data access time: 15ns

3200DX

Abstract: FCTD16C TA191 CNT4A AO11 TA273 dece2x4
Contextual Info: Macro Library Guide 1995 This document was created with FrameMaker 4.0.2 Actel Corporation, Sunnyvale, CA 94086  1995 Actel Corporation. All rights reserved. Part Number: 5029009-0 September 1995 No part of this document may be copied or reproduced in any form or by any means

Contextual Info: HIGH-SPEED 64K x 16 BANK-SWITCH ABLE DU AL-PORTE D SRAM WITH SEMAPHORE CONT ROLS ADVANCED IDT70728S/L FE ATURES: DESCRIPTION: • 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Eight independent 8K x 16 banks - 1 Megabit ot memory on chip • Fast asynchronous address-to-data access time: 15ns

XC4000E

Contextual Info: dsp_cmps.fm Page 103 Tuesday, July 14, 1998 8:04 AM 1’s and 2’s Complement July 17, 1998 Product Specification Pinout R Port names for the schematic symbol are shown in Figure 1 and described in Table 2. Xilinx Inc. 2100 Logic Drive San Jose, CA 95124

Contextual Info: HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH SEMAPHORE CONTROLS ADVANCED IDT70728S/L FEATURES: DESCRIPTION: • 64Kx 16 Bank-Switchable Dual-Ported SRAM Architecture - Eight independent 8K x 16 banks -1 Megabit of memory on chip • Fast asynchronous address-to-data access time: 20ns

WM8731

Abstract: 235K EH11
Contextual Info: WAN_0117 w WM8731/L Audio CODEC Supported Sampling Rates INTRODUCTION To generate the required DAC and ADC sampling rates, the WM8731/L provides for two modes of operation Normal and USB Modes. These two modes are programmed under software control in the Sampling Control Register R8, according to Table 1.

0A210

Abstract: 1004A wram nana electronics MAR95
Contextual Info: PRELIMINARY CMOS WINDOW RAM KM4232W259 DESCRIPTION FEATURES The KM4232W259 is a 1MByte Dual Ported DRAM array with added features that accelerate graphic operations in a GUI environment. A 256-bit internal bus allows transferring up to 32 bytes of data on a single chip.

ccir 624

Abstract: truth table pal 3.579
Contextual Info: C ir c u it D e s c r ip t io n Pin Descriptions This chapter begins w ith a table describing each pin and its function Table 1 , fol­ low ed by pinout diagram s o f each package (Figures 1 and 2), and a detailed func­ tional block diagram (Figure 3). Table 1. Pin Descriptions (1 o f 3)