4 INPUT BUFFER WITH ENABLE Search Results

Contextual Info: CY2DP1504 1:4 LVPECL Fanout Buffer with Selectable Clock Input 1:4 LVPECL Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to four LVPECL output pairs

Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to four LVDS output pairs

Contextual Info: SY54020R Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN and Fail-Safe Input 3.2Gbps, 2.5GHz General Description The SY54020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable /EN and Fail-Safe Input (FSI). The Enable is

Contextual Info: SY54020R Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN and Fail-Safe Input 3.2Gbps, 2.5GHz General Description The SY54020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable /EN and Fail-Safe Input (FSI). The Enable is

Contextual Info: SY54020R Product Brief Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN and Fail-Safe Input 3.2Gbps, 2.5GHz Description The SY54020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable /EN and Fail-Safe Input (FSI). The Enable is

Contextual Info: 100371 100371 Low Power Triple 4-Input Multiplexer with Enable Literature Number: SNOS433 100371 Low Power Triple 4-Input Multiplexer with Enable General Description The 100371 contains three 4-input multiplexers which share a common decoder inputs S0 and S1 . Output buffer gates

Contextual Info: SY54020R Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN and Fail-Safe Input 3.2Gbps, 2.5GHz Rev. 04/11/09-A1 General Description The SY54020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable /EN and Fail-Safe Input (FSI). The Enable is

Contextual Info: SY898533L Precision Differential 3.3V Low Skew LVPECL 1:4 Fanout Buffer General Description The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK

Contextual Info: SY898533L Precision Differential 3.3V Low Skew LVPECL 1:4 Fanout Buffer General Description The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 38-07142 Spec Title: CY2310ANZ 3.3V SDRAM BUFFER FOR MOBILE PCS WITH 4 SO-DIMMS Sunset Owner: Kelly Maas KVM Replaced by: None CY2310ANZ 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs Features Functional Description • One input to 10 output buffer and driver

3775 16 pin

Abstract: SY100EP15V SY100EP15VK4I SY100EP15VK4ITR
Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX FEATURES SY100EP15V Final DESCRIPTION • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle • < 225ps rise/fall times

Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX Micrel, Inc. ECL Pro SY100EP15V ECL Pro™ SY100EP15V FEATURES • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle

Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX Micrel ECL Pro ECL Pro™ SY100EP15V SY100EP15V FINAL FEATURES • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle

XEP15V

Abstract: k416 SY100EP15V SY100EP15VK4C SY100EP15VK4CTR SY100EP15VK4G SY100EP15VK4GTR SY100EP15VK4I SY100EP15VK4ITR
Contextual Info: Micrel, Inc. 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX ECL Pro SY100EP15V ECL Pro™ SY100EP15V FEATURES • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle

Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX ECL Pro SY100EP15V FINAL FEATURES • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle • < 225ps rise/fall times

Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX SY100EP15V FEATURES • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle • < 225ps rise/fall times • < 25ps within device skew

Contextual Info: 3* Section 5 Contents 54ACTQ/74ACTQ153 Dual 4-Input Multiplexer. 54ACQ/74ACQ240 Quiet Series Octal Buffer/Line Driver with TRI-STATE O u tp u ts . 54ACTQ/74ACTQ240 Quiet Series Octal Buffer/Line Driver with TRI-STATE O utputs

Contextual Info: DS40MB200 Dual 4 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis General Description Features The DS40MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data communication in FR4 backplanes up to 4 Gb/s. Each input stage has a fixed equalizer

Contextual Info: DS40MB200 Dual 4 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis General Description Features The DS40MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data communication in FR4 backplanes up to 4 Gb/s. Each input stage has a fixed equalizer

DS40MB200

Abstract: DS40MB200SQ
Contextual Info: DS40MB200 Dual 4 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis General Description Features The DS40MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data communication in FR4 backplanes up to 4 Gb/s. Each input stage has a fixed equalizer

U74AHCT1G126L-AF5-R

Abstract: U74AHCT1G126 U74AHCT1G126-AF5-R U74AHCT1G126-AL5-R SOT32-5 SOT325 sot 32-5
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD U74AHCT1G126 CMOS IC SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT 3 2 1 5 4 DESCRIPTION SOT-25 The U74AHCT1G126 is a single bus buffer gate with 3-state output controlled by enable input OE , When OE is LOW, the output is disabled.

U74AHCT1G125

Abstract: U74AHCT1G125-AF5-R U74AHCT1G125-AL5-R U74AHCT1G125L-AF5-R
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD U74AHCT1G125 CMOS IC SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT 3 2 1 5 4 DESCRIPTION SOT-25 The U74AHCT1G125 is a single bus buffer gate with 3-state output controlled by enable input OE , When OE is HIGH, the output is disabled.

Contextual Info: DATA SHEET ICS556-04 ICS556-04 LOW SKEW 1 TO 4 CLOCK BUFFER LOW SKEW 1 TO 4 CLOCK BUFFER Description Features The ICS556-04 is a low-skew, crystal input compatible clock buffer with oscillator. This device offers the lowest skew. • • • • • • See the ICS552-02 for a 1-to-8 low skew buffer. For

Contextual Info: W CY2318ANZ / CYPRESS 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs Features Functional Description • One input to 18 output buffer/driver The CY2318ANZ is a 3.3V buffer designed to distribute high-speed clocks in PC applications. The part has 18 outputs,