32-BIT PARALLEL-IN PARALLEL-OUT SHIFT REGISTER Search Results

LQFP_EP

Abstract: OSD19 OSD25 single chip osd
Contextual Info: 300 MHz, 32 x 32 Buffered Analog Crosspoint Switch ADV3200/ADV3201 Preliminary Technical Data FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM VPOS VNEG DVCC DGND CLK 193-BIT SHIFT REGISTER DATA OUT DATA IN 193 UPDATE CS RESET PARALLEL LATCH 192 SYNC-TIP CLAMP

OP28

Contextual Info: 500 MHz, 32 x 32 Buffered Video Crosspoint Switch AD8117 FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 VDD DGND A0 A1 A2 A3 A4 AD8117 SER/PAR 1 DATA IN 192-BIT SHIFT REGISTER WITH 6-BIT PARALLEL LOADING DATA OUT SET INDIVIDUAL, OR RESET ALL OUTPUTS TO OFF WE

HVO16

Abstract: M56692FP VH80
Contextual Info: MITSUBISHI <CONTROL / DRIVER IC> M56692FP Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER DESCRIPTION The M56692FP is a semiconductor integrated circuit that has a PIN CONFIGURATION TOP VIEW built-in, 32-bit shift register and a latch of CMOS structure with

shift register coding

Abstract: 32-bit shift register shift register ISL5216 AN9987
Contextual Info: IEEE Standard Test Access Port and Boundary Scan Register for the ISL5216 QPDC TM Application Note November 2001 AN9987.1 Russell Davidson & Dejan Radic Introduction: The test access port (TAP) provided on the ISL5216 is compliant with the IEEE Std 1149.1-1990 TAP. The purpose

MSM6355GS

Abstract: lcd screen pin out LDXX
Contextual Info: OKI Semiconductor MSM6355 D O T M A TR IX L C D C O N T R O L L E R GENERAL DESCRIPTION The MSM6355GS is a controller for large dot matrix liquid crystal displays. Since the configuration of the internal register is based on the MSM6255, it is compatible with the MSM6255 in software

PIN DIAGRAM OF 7 segment display LT 543

Abstract: 7 SEGMENT DISPLAY LT 543 LT 543 7 segment display 7 SEGMENT LT 543 MD4332BE MD4332B lt 543 display 32-bit shift register MD4332BC
Contextual Info: MD4332B 32 Segment LCD Driver CMOS MITEL8 Feb. 1985 Features Pin Connections • CMOS Low power. • 3 to 18 volt operation. • On-chip wave-shaping. • High-speed typ. 3 MHz shift register. T/C Dl NC Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15

hvo32

Abstract: HVO16 M56693
Contextual Info: MITSUBISHI <CONTROL / DRIVER IC> M56693FP/GP Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER DESCRIPTION The M56693 is a semiconductor integrated circuit that has a built- PIN CONFIGURATION TOP VIEW in, 32-bit shift register and a latch of CMOS structure with serial

Contextual Info: a CtT7A i T O ' 41 Serializing First-In First-Out (FIFO 64 x 8/9 Memory Features/Benefits • High-speed 28-MHz serial shlft-ln/shilt-out rate Advanced Micro Devices Ordering Information • 10-MHz parallel shlit-ln/shlft-out rate Part Number Package Temp

Contextual Info: MITSUBISHI cCONTROL/ DRIVER IC> M56692FP Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER DESCRIPTION The M 56692FP is a sem iconductor integrated circuit that has a PIN CONFIGURATION TOP VIEW built-in, 32-bit shift register and a latch of CM O S structure with

lattice 1996

Contextual Info: Specifications ispLSI and pLSI 6192 ® ispLSI and pLSI 6192 High Density Programmable Logic with Dedicated Memory and Register/Counter Modules — 96 I/O Pins with Input Registers — Security Cell Prevents Unauthorized Design Copying Features • A FAMILY OF HIGHLY INTEGRATED, CELL-BASED,

SERIAL INPUT PARALLEL 18 pin

Abstract: CXB1135Q CXB1135
Contextual Info: CXB1135Q S O N Y Advanced Information 16 to 8 bit Serial Comparator Description C X B 1 135Q is an Ultra high speed bipolar monolithic serial comparator IC, which operates in 8 to 16 bit length mode. Th is IC compares serial data inputs of shift register with preseted parallel data and indicates

digital IIR Filter VHDL code

Abstract: verilog code for fir filter using DA vhdl code for 8-bit serial adder low pass Filter VHDL code low pass fir Filter VHDL code verilog edge detection 2d filter xilinx xilinx code for 8-bit serial adder 8 bit sequential multiplier VERILOG 8 bit fir filter vhdl code implementation of 16-tap fir filter using fpga
Contextual Info: SEMINAR SIGNAL PROCESSING with XILINX FPGAs Bruce Newgard N BITS WIDE FIR FILTER SAMPLE DATA X0 SUM X • K C0 X11 X • C1 X22 OUTPUT DATA X • C22 • • • • • • K SUMs K TAPS LONG X.D.S.P. 6OLGH1XPEHU  ;'63337 SIGNAL PROCESSING WITH XILINX FPGAs

A15V

Abstract: PIS01
Contextual Info: C 7^17 0 / 4 1 / Serializing First-In First-Out FIFO 64 x 8/9 Memory Advanced Micro Devices Ordering Information Features/Benefits • High-speed 28-MHz serial *hlft-ln/*hitt-out rate • 10-MHz parallel *hltt-in/$hlft-out rate Part Number Package Temp Description

Contextual Info: ispLSI 6192 High Density Programmable Logic with Dedicated Memory and Register/Counter Modules — 96 I/O Pins with Input Registers — Security Cell Prevents Unauthorized Design Copying Features • A FAMILY OF HIGHLY INTEGRATED, CELL-BASED, PROGRAMMABLE LOGIC DEVICES CONSISTING OF:

TAA 141

Abstract: TAA141 6192F SEL02
Contextual Info: ispLSI 6192 High Density Programmable Logic with Dedicated Memory and Register/Counter Modules — 96 I/O Pins with Input Registers — Security Cell Prevents Unauthorized Design Copying Features • A FAMILY OF HIGHLY INTEGRATED, CELL-BASED, PROGRAMMABLE LOGIC DEVICES CONSISTING OF:

C3745

Contextual Info: a 32-Channel Infinite Sample-and-Hold AD5533* GENERAL DESCRIPTION The AD5533 combines a 32-channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, VIN, is sampled and its digital representation transferred to a chosen DAC register. VOUT for this

C3745

Abstract: AD5532ABC-1 AD5532ABC-2 AD5532ABC-3 AD5532ABC-5 AD5533 AD5533ABC-1 AD780 EVAL-AD5532EB VO17
Contextual Info: a 32-Channel Infinite Sample-and-Hold AD5533* GENERAL DESCRIPTION The AD5533 combines a 32-channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, VIN, is sampled and its digital representation transferred to a chosen DAC register. VOUT for this

STK 3240

Contextual Info: 1 0 1992 [^ Im #iPD77016 SPRX 16-Bit Fixed-Point Digital Signal Processor j W NEC Electronics Inc. Preliminary Information_ Description ThejL/PD77016 is the first digital signal processor (DSP) of the SPRX family. It is a high-performance, generalpurpose, 16-bit fixed-point, register-based DSP that is

MD4332BE

Contextual Info: CMOS M D4330B/M D4332B 30/32 Segment LCD Driver FEB. 1985 Features • • • • C M O S Low power 3 to 18 volt operation On-chip wave-shaping High-speed typ. 3 MHz shift register • Std. 40-pin Dual-ln-Line packages Pin Names Pin Connections MD4330B

32-Bit sipo Shift Register

Abstract: vx-4321 DL140 MC100SX1451FI100 PEP VME
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA AutoBahn   Spanceiver 100MByte/s Version MC100SX1451FI100 The MC100SX1451FI100 AutoBahn chip is a high–speed serial– to–parallel, parallel–to–serial transceiver. The AutoBahn can be used to implement a high–speed, half–duplex, bi–directional serial data link with

Contextual Info: Advanced Micro Devices ° H 1' Serializing First-In First-Out FIFO 64 x 8/9 Memory Ordering Information Features/ Benefits • High-speed 28-MHz serial shift-ln/shlft-out rate • 10-MHz parallel shlft-ln/shift-out rale Part Number Package Temp Description

SN74LS166

Abstract: 74LS LS166 SN74LS166D SN74LS166DR2 SN74LS166M SN74LS166MEL SN74LS166N
Contextual Info: SN74LS166 8-Bit Shift Registers The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified.

cake power

Abstract: 0X00 Floating-Point Arithmetic saturate "saturation arithmetic"
Contextual Info: AltiVec AltiVec™ Technology Technology ➤ On May 7, 1998, Motorola disclosed a new technology which integrates into the existing PowerPC Architecture a new high bandwidth, parallel operation vector execution unit ➤ Motorola’s new AltiVec™ technology expands the capabilities of

Contextual Info: Lattice ispLSI 6192 " ; Semiconductor • ■ ■ Corporation High Density Programmable Logic wjth Dedicated Memory and Register/Counter Modules — 96 I/O Pins with Input Registers — Security Cell Prevents Unauthorized Design C opy­ ing Features • A FAMILY OF HIGHLY INTEGRATED, CELL-BASED,