319Q Search Results

GH1-319QA

Abstract: GH1-219QG GH1-419QC GH1-419QF
Contextual Info: 页码，1/1 GH1电感式接近开关 19 8 外形编号 检测距离Sn[mm] 具 备 型 号 NPN 常开 GH1-319QA NPN 常闭 GH1-319QB NPN 一开一闭 GH1-419QC DC PNP 常开 型 PNP 常闭 GH1-319QD GH1-319QE PNP 一开一闭 GH1-419QF 二线制 常开

CY37384

Abstract: CY37384V L0651
Contextual Info: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.

Contextual Info: CY7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

Contextual Info: PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpp - 15 ns, tc o — 10 ns, tg = 12 ns — Military: tpp = 20 ns, tc o = 15 ns, tg = 15 ns CMOS Generic 24-Pin Reprogrammable Logic Device • Generic architecture to replace stan­ dard logic functions including: 20L10,

Contextual Info: CY7C372 PRELIMINARY CYPRESS SEMICONDUCTOR 64-Macrocell Flash PLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed The CY7C372 is a Flash Erasable Pro­

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin

Contextual Info: w ~ CYPRESS Features • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • In-System Reprogrammable ISR Flash technology — JTAG interface • No hidden delays • High speed — f M A X = 143 MHz — tpD= 8*5 ns

Contextual Info: UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 m acrocells in four logic blocks T h e CY7C373 is a Flash erasable Com plex Program m able Logic Device C PL D and is p a rt o f th e F lash 370 ” family o f highdensity, high-speed C PLD s. Like all m em ­

Contextual Info: 32-Macrocell Flash CPLD Features Functional Description • 32 macrocells in two logic blocks The CY7C371 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the F lash370 ” family of highdensity, high-speed CPLDs. Like all mem­

ZUA15

Abstract: ZUA12
Contextual Info: HM62W1400H Series 4194304-word x 1-bit High Speed CMOS Static RAM HITACHI ADE-203-773 Z Preliminary Rev. 0.0 Apr. 28, 1997 Description The HM62W1400H is an asyncronous high speed static RAM organized as 4-Mword x 1-bit. It has realized high speed access time (10/12/15 ns) with employing 0.35 (Am CMOS process and high speed circuit

7c331-35

Contextual Info: s :^é= , CY7C331 •jS QYPRESS -■ W SEMICONDUCTOR Asynchronous Registered EPLD Features • TVelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

allocator

Contextual Info: CY7C373Ì PRELIMINARY UltraLogic 64-Macrocell Flash CPLD Features Device CPLD and is part of the FLASH370i™ family of high-density, high­ speed CPLDs. Like all members of the F lash 37(H family, the CY7C373i is de­ signed to bring the ease of use and high

IP PLC

Contextual Info: fax id: 6007 F or new d esig ns, p lease re fe r to th e P A LC E22V10. PALC22V10D p yp: v « *1 X X Flash Erasable, Reprogrammable CMOS PAL Device - vid es the capability of de fining th e a rch itecture of each output individually. Each of th e 10 p o te n tia l outputs m ay be specified

Contextual Info: y PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpo = 15 ns, tco — 10 ns, ts = 12 ns — Military: tpo = 20 ns, tco = 15 ns, ts = 15 ns • Low power — Ice max.: 70 mA, commercial — Ice max.: 100 mA, military • Commercial and military temperature

Contextual Info: fax id: 6137 CY7C372Î C'i- UltraLogic 64-Macrocell Flash CPLD Features FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the Fi_ASH370i family, the CY7C372i is de­ signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to

37-25615

Abstract: CY37256 CY37256P160-125UMB
Contextual Info: UltraLogic 256-Macrocell ISR™ CPLD Features — tCo = 4 -5 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 256 macrocells in sixteen logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

CY37512

Contextual Info: UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

Contextual Info: CY7C332 ¡W CYPRESS SEMICONDUCTOR 13 in p u t m acrocells, each having: — C om plem entary input — R egister, latch, o r tra n s p a re n t access — Two clock sources Features • • Registered Combinatorial EPLD 12 I/O m acrocells each having: — R egistered, latched, o r tra n s p a re n t

Contextual Info: CMOS SRAM KM64V1003B 256K x 4 Bit with OE High-Speed CMOS Static RAM(3.3V Operating) FEATURES G E N E R A L D E S C R IP T IO N • Fast Access Time 8,10,12ns(Max.) • Low Power Dissipation Standby (TTL) : 50mA(Max.) (CMOS): 5mA{Max.) Operating KM64V1003B - 8 : 150mA(Max.)

Contextual Info: PRELIMINARY 128Kx36 Synchronous SRAM KM736V790 128Kx36-Bit Synchronous Pipelined Burst SRAM R e v . N o. H is to ry D ra ft D a te 0.0 Initial draft December. 15. 1997 0.1 Change speed symbol 6.0/6.7/7.5/8.5 to 60/67/75/85, February. 02. 1998 R e m a rk Change 7.5 bin to 7.2

Contextual Info: Features « 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — fMAx = 100 MHz — tpo = 12 ns — ts = 7 ns " tco = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin

Contextual Info: CY7C372 PRELIMINARY CYPRESS 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed — fMAX - 125 MHz — tpD - 10 ns

tlO41

Abstract: 7C373-125 CY7C373 CY7C374 FLASH370 Wo2c
Contextual Info: CYPRESS Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f M A X = 12S MHz — tpo = 10 ns — ts = 5.5 ns — tc o = 6-5 ns • Electrically alterable Flash

I8272

Abstract: 20RA10 20RA10-15 PLDC20RA10 HP 2502 470S3 HP 2502 8 pin PLDC20RA10-30WC
Contextual Info: CYPRESS 4bE SEMICONDUCTOR SSfl^tiba D -i*\ -O c\ 'TH □ OÜb'îSM G E3CYP PLDC20RA10 CYPRESS . .— — Features Advanced-user programmable macro* cell CMOS EPROM technology for repro­ grammability Up to 20 Input terms 10 programmable I/O macrocells Output macrocell programmable as