2X32MX16BIT Search Results

2X32MX16BIT Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
DDR200 Abstract: DDR266 DDR333 DDR400 W3E232M16S-XSTX Contextual Info: White Electronic Designs W3E232M16S-XSTX PRELIMINARY* 2x32Mx16bit DDR SDRAM Bidirectional data strobe DQS transmitted/ received with data, i.e., source-synchronous data capture (one per byte) FEATURES Double-data-rate architecture; two data transfers per clock cycle	Original	w3e232m16s-xstx 2x32mx16bit 66pin 64mx16bit +4ddr200 ddr266 ddr333 ddr400	PDF
DDR400 Abstract: 400st Contextual Info: White Electronic Designs W3E232M16S-400STCG PRELIMINARY* 2x32Mx16bit DDR SDRAM FEATURES Bidirectional data strobe DQS Double-data-rate architecture; two data transfers per clock cycle DQS edge-aligned with data for READs; centeraligned with data for WRITEs	Original	w3e232m16s-400stcg 2x32mx16bit 66pin 2x32m +4ddr266 ddr333 ddr400 400st	PDF

Catalog Datasheet

Type

Document Tags

PDF

DDR200

Abstract: DDR266 DDR333 DDR400 W3E232M16S-XSTX
Contextual Info: White Electronic Designs W3E232M16S-XSTX PRELIMINARY* 2x32Mx16bit DDR SDRAM Bidirectional data strobe DQS transmitted/ received with data, i.e., source-synchronous data capture (one per byte) FEATURES Double-data-rate architecture; two data transfers per clock cycle

Original

w3e232m16s-xstx 2x32mx16bit 66pin 64mx16bit +4

PDF

DDR400

Abstract: 400st
Contextual Info: White Electronic Designs W3E232M16S-400STCG PRELIMINARY* 2x32Mx16bit DDR SDRAM FEATURES Bidirectional data strobe DQS Double-data-rate architecture; two data transfers per clock cycle DQS edge-aligned with data for READs; centeraligned with data for WRITEs

Original

w3e232m16s-400stcg 2x32mx16bit 66pin 2x32m +4

PDF